Various issues with alt2gxb and altlvds_tx

[Altera_Forum]

Hi all, 

 I have a simple and quite stupid doubt with the embedded high speed transmitters/receivers in a Stratix IV. I want to bypass all the modules (the 8b/10b encoder, etc...) and just use them as a serdes. If I do that can I transmit a totally arbitrary sequence? Let´s say, a long chain of 1´s or 0´s? I have tried a simple simulation with alt2gxb and modelsim and I got some weird results trying to serialize 16 bits (all ones or all zeros).   I wanted to use the LVDS serdes for the same purpose; is that possible? I am also running into a Quartus issue that stops me from instantiating the megafunction. I will post that in the quartus II section, but if anyone has ran into this and knows a solution please let me know.  Obviously it is the first time I try to use these blocks, so any help would be appreciated.  Thanks in advance!

[Altera_Forum]

The fact you can transmit a totally arbitrary sequence is not related by the tool, but on how electrically you connect the transmitter and the receiver. 

If the links are AC connected, you NEED to use a balanced protocol because else the Capacitor at some point is fully charged. An example maybe clarify a little bit. Suppose you transmit a very long sequence of '1', at that point you'll have that the capacitor is fully charged, now if you want to transmit only a single '0' and then continue with the 1 sequence that means you of course on the receiver side do not see it, because that only single zero last to few times in order to discharge the capacitor to a level that is seen as '0' by the receiver.  This is always more true more frequencies are higher.  I hope it clarify a little bit.  Ok now the other issue: all 1 or all 0. Serdes has to recover clock and that is done from the data transitions. If data do not have transition you cannot recover the clock. Moreover if you transmit all time 0 or 1, you could use a TTL line :)  Another issue is that once the clock is recovered (and it depend from PLL time, first it lock to clock reference you provide and then he start to lock to data) you can imagine that receiver start to see an infinite sequence of 1 and 0 but depending on its locked time, receiving board turn on time respect sending board and other, he need a way to understand where are the boundaries of these bits that he is receiving, told in another way which is the first bit that has to be used to fill the word registers of the widht you specified.   Ok I hope it is a bit clearer now, in any case you can have a look at  http://www.altera.com/education/training/curriculum/high-speed_io/trn-high-speed_io.html Have a look at TRANSCEIVER BASIC course on that page   These are online FREE course from Altera web site: They are very nice done imo. You can find them from www.altera.com then go on learning section and then training course :)

[Altera_Forum]

Hi Darkwave, 

 thanks a lot for your answer. It was clear to me that if I AC couple it does not make sense to transmit long sequences of 1's and 0's. So no, I do not want to AC couple anything. I also don't care about receiving the data.   Actually to make my point a little bit clearer, there is no data to transmit. I just need to be able to accurately time transitions in my signals. An example: I use 1 Gbps speed (1 bit, 1 ns); for 100 ns I want to keep my output high (so I send all 1's) but at exactly t=100 ns I pull it low (send a 0), which lasts for the minimum amount of time possible (that is, around 1 ns) and then the signal goes high again.   I want to use the transmitter because it allows me to obtain such resolution, but there is no receiver. I am wondering if I can do that with the FPGA and its transmitter / receiver circuitry or not. Or if I can just use the LVDS serdes.  And I had already gone through the course, it was actually pretty useful but it deals more with "conventional" use of the system.