about ram_2_port ip core

[Altera_Forum]

In my project I used the ip core (ram_2_port).I add avalon_tristate_slave for the ram2port in the sopc builer.But I can't write to the ram2port_base.When I write 0x00 to the ram2port_base,it write to the (ram2port_base+2).why?

[Altera_Forum]

are the data widths of the master and slave the same? is the component a register slave or a memory slave, ie is it using dynamic bus sizing? 

 --dalon

[Altera_Forum]

is memory slave and dynamic bus sizing.The data width of ram2port is 16,address width is 9.how to configure the avalon tri-state slave timing for ram2port in the new component editer<interfaces>?

[Altera_Forum]

i don't believe x9 interfaces will work unless the master is x9 as well. 

 --dalon

[Altera_Forum]

here are my picture of my project. 

  http://www.qudoo.net/p?id=4028808e14ad4f050114af6350160c47&size=m http://www.qudoo.net/p?id=4028808e14ad4f050114af6350940c49&size=m http://www.qudoo.net/p?id=4028808e14ad4f050114af6351300c4b&size=m http://www.qudoo.net/p?id=4028808e14ad4f050114af6351fb0c4d&size=m I want to know how to configure the timing of the ram2port?

[Altera_Forum]

that looks good, but remember, if you are using a 32 bit master to issue the read, it will actuall perform 2 reads to get the 32 bit data, this could be the cause of address 0x2 being driven.

[Altera_Forum]

I don't know the timing request of ram2port.I can't find it at its datasheet.I think the reason that I can't write the data to the first address of ramport is the timing .