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i want to write a state machine.but quartus ii report error.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity p159 is port( clk,clr,input:in std_logic; output:out std_logic_vector(3 downto 0)); end p159; architecture b of p159 is type ss is(s0,s1,s2,s3); signal s:ss; begin p1:process(clk,clr) begin if clr='0' then s=s0; elsif clk'event and clk='1' then case s is when s0=>if input='0' then s=s1; end if; when s1=>if input='1' then s=s2; end if; when s2=>if input='1' then s=s3; end if; when s3=>if input='0' then s=s0; end if; end case; end if; end process p2:process(state) begin case s is when s0=>output<="0010"; when s1=>output<="1001"; when s2=>output<="1100"; when s3=>output<="1110"; end case; end process; end b; Error (10500): VHDL syntax error at p159.vhd(15) near text "="; expecting "(", or "'", or "." i can't understand.Link Copied
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its a syntax error on line 15 (actually, theres more than that).
the error is here: if clr='0' then s=s0; it needs to be s <= s0; in VHDL <= is used for assignment of signals, := for variables. = is just an equality operator.- Mark as New
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thank you very much
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