about verilog code" while"

[Altera_Forum]

hi all: 

One of my books says that we can compile "while" if there is some thing control it (eg:@(posedge Clock)).I don't know whether my book is right. Is there some one have do it .

[Altera_Forum]

reg MyRegBit; 

always @ ( posedge MyClock )  MyRegBit <= MyAssignedValue;  this is like a  while ( 1 )  { MyRegBit = MyAssignedValue; }  if you want dependencies based upon a signal then while ( EnableAssignment )  { MyRegBit = MyAssignedValue; }  would be reg MyRegBit; always @ ( posedge MyClock ) if ( EnableAssignment )  MyRegBit <= MyAssignedValue; else  MyRegBit <= MyRegBit;  or write it like reg MyRegBit; always @ ( posedge MyClock )  MyRegBit <= ( EnableAssignment ) ? MyAssignedValue : MyRegBit;