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hi,
my design contains some parametrized functions memories like altsyncram..when i tried to synthesize my design, the synthesizer treat this function as a black box, and in the post synthesized netlist file, this function is instanciated and it is not replaced with basic ram blocks of the FPGA device(like M9K, M144K).. i'm asking if there is a way to synthesis my design in a lower level, so that this altsyncram is replaced with the equivalent resources used in the FPGA device?? thank you in advanceLink Copied
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--- Quote Start --- ... the synthesizer treat this function as a black box ... --- Quote End --- In the MegaWizard for the RAM component, if you leave the implementation as "AUTO", then the tool will select the RAM. You can however select a specific type of RAM. Even if you instantiate the altsyncram component directly in VHDL or Verilog, you can create a couple of example instances using the MegaWizard to determine the correct values for the generics. Cheers, Dave
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