clock domain crossing between two PLLs (cyclone III)

[Altera_Forum]

hello! 

I use two PLLs in my design. One is reconfigurable and the the other one is not. If I use both PLLs to control one single circuit I always get trouble. (Example: The reconfigurable PLL generates tigger events while the other PLL feeds the clock into the circuit) Even if both PLLs are implemented in source synchronous mode. I thought this setting makes the signals of both PLLs synchronous - as if generated from one PLL.  How can I prevent missing trigger events or even completly freezing state machines?  Thanks in advance! Sören

[Altera_Forum]

The latest after reconfiguring one PLL or setting diiferent frequencies, the clocks can't be synchronous any more. But individual binary signals can be easily synchronized by two DFFs, multi bit signals are more difficult, needing handshake synchronization or domain crossing FIFOs.

[Altera_Forum]

Many thanks for your reply! Unfortunately its not possible to use double flops for me (at least not everywhere I've got crossing clock domains) because I have to control very fast processes. 

 But with that knowledge I can try to avoid such problems by taking care in the design process.

[Altera_Forum]

--- Quote Start ---  The latest after reconfiguring one PLL or setting diiferent frequencies, the clocks can't be synchronous any more. But individual binary signals can be easily synchronized by two DFFs, multi bit signals are more difficult, needing handshake synchronization or domain crossing FIFOs.  --- Quote End ---    Single bit or multibit can be synchronised by two stage registers. There is no difference between the two cases.  I think what you mean is that slow events can do with this synchroniser only while fast events like data buses changing every clock need also handshaking signals as in dc fifos

[Altera_Forum]

--- Quote Start ---  Single bit or multibit can be synchronised by two stage registers. There is no difference between the two cases.  --- Quote End ---   I think, there's an important difference. Consider a two bit signal changing from "01" to "10". When synchronizing the signal with registers only, the receiver may read "00" or "11" once during the transient due to delay skew. You have to implement additional filter logic, e.g. wait until the signal has been read twice with identical result, or handshake. For incrementally changing counter values, e.g. a FIFO level, gray encoding is a solution.  Referring to the original question, it isn't clear if the two clocks can be possibly synchronized, or if the frequency ratio would prevent an synchronous transfer anyway.