For our 10G board based on the Altera’s FPGA Stratix IV GT require the connection of transceiver with LVPECL output to Stratix IV GT high-speed receiver by using the DC[/B][/B] coupling (burst signal).
So which are recommendations of Altera for this case?
Is it acceptable the circuit performs termination of LVPECL signal and shifting the signal offset from LVPECL(2V) to LVDS(1.2V)? (see attachment file)
Thank you
