error -- Flash & NIOS2

[Altera_Forum]

Hello to all, 

 i built a stand alone electronics with an EP2C8 fpga and an 2MB flash-ram. I flashed my EPCS4 device with my current design. By the way, i purchased a license for MegaCore functions and i have installed the license.  Now i want to flash the ram with the NIOS2 Flash Programmer, but it doesn't work. I got always the same error message.:(  #!/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.#   cd C:/altera/FPGA_Projecte/Prj_ARCUS-ORBITER_FlashTest/software/hello_world_0/De bug # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00200000 --end=0x3fffff --reset=0x40200 0 --input="hello_world_0.elf" --output="cfi_flash.flash" --boot="C:/altera/81/ip /altera/nios2_ip/altera_nios2/boot_loader_cfi.srec" # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00200000 --sidp=0x00405010  --id=1624484866 --timestamp=1246526067 "cfi_flash.flash" There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.  Have you guys any suggestions to solve this problem???  Many thank's for your help...  Manuel 

[Altera_Forum]

Check that the values you give to the flash programmer (--sidp=0x00405010 

--id=1624484866 --timestamp=1246526067) are consistent with theSopc system that is currently in your FPGA.

[Altera_Forum]

Are you sure your FPGA is actually getting programmed with your image from the EPCS4? Can you program the FPGA via JTAG and then try the flash download? 

 Jake

[Altera_Forum]

Thank's Daixiwen for your fast reply. You are right, there is a difference between sopc timestamp and flash timestamp, but i don't know how I can match these two timestamps to be the same...

[Altera_Forum]

Hello jakobjones, I think my fpga is programmed with the current image, because I placed a simple-counter device on it, whitch has nothing to do with the NIOS2 processor. This counter drives an output, and I tested it with my osciloscope... 

It works fine.

[Altera_Forum]

You need to get the actual ID values from your SOPC system. If you look in your quartus project folder, you should find the datasheet for your SOPC system. The file has the same name than the SOPC project, but with an html extension. 

There you'll see a box model of the SOPC system, with a list of peripherals. Look for the one that's f the type altera_avalon_sysid and remember its name. In my case it's sysid. Just underneath you have the address map. Find the address for the sysid component, and this value is the one that you must provide with the sidp argument to nios2-flash-programmer. Then scroll down to the description of the sysid component, and there you'll find the id and timestamp values that you must provide to nios2-flash-programmer.  And as said Jake, ensure that the same SOPC system is currently running in the fpga before you run nios2-flash-programmer

[Altera_Forum]

Are you using the NIOS II IDE to program the flash? If so, it should be getting these values automatically from your PTF file. So if it's not, then you have a problem. I'd check to make absolutely sure your system library and software project are pointing to the right PTF file. 

 Jake

[Altera_Forum]

Daixiwen, I have a bigger problem than I thought, because my SOPC builder will not generate a *.html file... ,but you are right, regarding to the SOPC handbook there must be a file with the html extension. I have checked the *.ptf, and the confusion is, that the timestamp in this file doesn't match with the timestamp in my SOPC gui. 

Jake thank's for your reply, I have built a completely new testproject and a new project folder on an other harddrive. I have controlled the timestamp in my *.ptf file and the the timestamp in my system.h file. They were equal... so I think it is the same ptf file, int't it? The next step I would try, is to download and to install the new Quartus2 and Nios2 software. I hope that will solve this problem. You will hear from me...

[Altera_Forum]

What version of Quartus do you have? I think the *.html generation was introduced in Quartus 8. You can also find this information in the system.h file, as you did. I just find the html more human readable ;) 

If the values are equal it means that the software was compiled with the correct ptf file. Now you must also ensure that you compile the FPGA design with the same SOPC definition, and download the compiled sof file in the FPGA.

[Altera_Forum]

I have the 8.1 version of quartus2. I have taken some screenshots for a better explaination of my design chain.  

 In PIC1 you see the sopc builder gui with the actuall design. Take a look to the pop up with the current timestamp and note the designname "...\processor.sopc  After generation i placed the processor in my schematic and complied it. Now I have to convert the *.sof file in a *.pof file (in my case TestFile.pof) for a EPCS4 device. PIC2  In PIC3 you see the message of a successfull programming operation. Now the design should run on the fpga.   After that, I checked the processor.ptf file (PIC4) and the system.h file (PIC5). Both timpestamps are equal, but if you compare it with the timestamp in PIC1 you will see a mistake. They doesn't match. :( Could it be???   p.s. many thank's for your help...

[Altera_Forum]

I assume that you took the PIC1 picture before you generated the SOPC system? If yes you need to take it after. The timestamp is changed each time you generate the system. If you look at it after the generation you should see the same value everywhere.

[Altera_Forum]

OK, you are right, every time you generate a sopc file you get a new timestamp. After your reply I opened with a double click the processor design. 

At the same time I opened the processor.ptf file. (PIC_before) I got two timestamps: 1246880377 - SOPC 1246873243 - PTF  I generated a new design, with a click on GENERATE. After then I opened once more with a simple double click the processor design and once more the processor.ptf file. (PIC_after) The two timestamps were: 1246880917 - SOPC 1246880377 - PTF  And that's not enought. One time more generation and compare: (PIC_after_after) 1246881421 - SOPC 1246880917 - PTF  After generation I get from the sopc builder a new timestamp and the old one is in my *.ptf file... :confused: 

[Altera_Forum]

I think I have done a mistake. Each time you enter the sopc builder, you'll get a new timestamp. I think I have a problem with my jtag download cable...

[Altera_Forum]

Yes, nobody is perfect, especially if it is the first design... and thank's daixiwen for your patience.

[Altera_Forum]

That's really odd. I can't reproduce what you are describing... I have the same timestamp in the ptf and the sopc system. 

Don't you do anything else after the generation? Something that would make SOPC builder think that you changed something in your system?

[Altera_Forum]

No, I have done nothing after the generation. I think, I solved this problem... 

At the first time I would flash the eeprom with the nios2 programm, but it doesn't work. ID error etc., because the jtag connection to my fpga had a fault. I realized it than I tried to flash the nios2 programm in the on_chip memory. I got the same ID and timestamp error as before. This morning I found the mistake and now it works. But could you tell me what a cfi table is ?   #!/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.#   cd C:/Programm_ARCUS-OBITER_Handheld/software/hello_world_small_0/Release # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00200000 --end=0x3fffff --reset=0x40400 0 --input="hello_world_small_0.elf" --output="cfi_flash.flash" --boot="C:/altera /81/ip/altera/nios2_ip/altera_nios2/boot_loader_cfi.srec" # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00200000 --cable='USB-Blas ter [USB-0]' --device=1 --sidp=0x00409030 --id=1732617863 --timestamp=1246886060  "cfi_flash.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x00409030: verified <--- jipiiiie No CFI table found at address 0x00200000 Leaving target processor paused

[Altera_Forum]

The error message probably means that it's not able to communicate with the flash. Are you sure it is well connected? 

You can also use a SignalTap II probe and see if the signals going to/from the flash are as expected.

[Altera_Forum]

Yes, I think so. I have a AT49BV163DT connected. The times for settling etc. in the sopc builder gui are set to 100 ns. I think a longer time than needed shouldn't be a problem. Suspicious is the one time write access to the flash ram. (PIC_Signal) There should be more than one write access, shouldn't it???

[Altera_Forum]

You should have a special write (data 98h to address 55h) to enter CFI mode. It may come a lot later in your curve. Can you increase the buffer size and reduce the sampling clock frequency? 

Or a better way could be to divide the buffer in several zones, each one of them triggered on an access.

[Altera_Forum]

I'll try both. I have a 1MHz source on my board. I have also checked the hardware connection between the ram and the fpga. The reset pin has allways high signal, I hope that's okay. Could we find out more with the nios2 flash programmer command line mode ???

[Altera_Forum]

Could you take a look at the screen shot? On the right screen you will see  

the read content of the flash-ram. I think the flash-ram works correctly. But on the left screen you see that the programming sequence failed. Could it be, the read sequence works and the write sequence doesn't???