- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
please provide me with some suggestions ASAP.
Link Copied
3 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- please provide me with some suggestions ASAP. --- Quote End --- You will only get ASAP responses if you take the time to describe what you want to do. How many transceivers, what frequency, etc? What IP, eg. CPRI? Show people that you've at least tried to look at the documentation, and you will then get some reasonable feedback. The devices that have transceivers are the low-range Cyclone GX, mid-range Arria, and high-end Stratix GX/GT. Cheers, Dave
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks for tht ....
i have developed the lte layer 2 which works for the frequencies between 3 MHZ to 20 MHZ ..... so i need to implement this all layer coding on FPGA with one transceiver as a base station and othr as an user equipment .... so m confused which kit should i work on .... i have seen stratix v kit with it requirement ... help me if u can with this ...- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- i have developed the lte layer 2 which works for the frequencies between 3 MHZ to 20 MHZ ..... so i need to implement this all layer coding on FPGA with one transceiver as a base station and othr as an user equipment --- Quote End --- You still haven't explained what the operating characteristics of your transceivers are. I've never looked at LTE requirements, and many others with transceiver experience may not have either. I am sure Altera has some application note, or MegaCore users guide, explaining some of this stuff. Try and have a look at their documents. If you can explain what you want to do with the transceiver in terms of clocking, encoding requirements (8B/10B ), input/output data widths and rates, number of lanes, etc., then we can suggest FPGA families. Cheers, Dave
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page