interface with DDR external memory using IP-core

[Altera_Forum]

Hi all! 

 I'm working with Cyclone V, my aim is to use DDR memory. Am I right that I need to create my own controller and use ALTDQ_DQS2 IP Core as PHY? I mean that Altera removed support of DDR memory controller in Cyclone V.

[Altera_Forum]

Correct, Altera DDR controller is not supported on Cyclone V. 

 If this is a new design, my suggestion would be to use Cyclone V with Hard Memory Controller and select a compatible memory device.

[Altera_Forum]

Thanks for your answer, ted. 

 No, design hasn't the ability to use HMC. I think that I have to use ALTDQ_DQS2 and custom VHDL_or_Verilog Controller