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Valued Contributor III
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invert clock at output pin in DDR3 uniphy controller

Hi, 

I am using DDR3 uniphy controller in startixV(with Quartus 15.1). 

In PCB board design, the clock is mistakely swaped at output, that is, ck at fpga pin is connected to ck# at ddr3 pin. 

 

Is there any way to swap clock output or invert clock at fpga side just at the output safely?  

i mean revise the source code at fpga side, i find that xilinx could do this, so i think altera can do it also, but i can not find where i can safely change the code to achieve my purpose. 

 

Many thanks! 

 

ingdxdy
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Valued Contributor III
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Are you using Hard DDR-3 Controller or Soft?

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Valued Contributor III
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thanks for your reply. 

 

 

--- Quote Start ---  

Are you using Hard DDR-3 Controller or Soft? 

--- Quote End ---  

 

 

i am using soft ddr3 ip core(with quarter rate mode). 

 

Best Wishes, 

ingdxdy
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Valued Contributor III
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I think this will depend on which pins your DDR3 clock comes from. They typically come out on the dedicated 'PLL_OUT' pins, directly from the low latency PLL output signals. Assuming they do then there's no method of inverting them between the PLL and the pins. 

 

If they don't come out of these dedicated pins then you should be able to invert them. However, this has further implications as the delay out of the device will be far less determinate and may well compromise the DDR functionality in a different way. 

 

In the UniPHY there is an option, in the 'Board Settings' tab, to specify the 'Maximum CK delay to DIMM/device'. You could try adding half your clock period to whatever value you have in there. This may cause a change to the PLL settings to work in your favour. I hope this would change the relative position of the clock at the start of DDR3 training and, hopefully, allow the UniPHY and PLL to find a working solution. 

 

I would also say this is worth asking Altera directly about as well. Open a case through myAltera. They seem to be on the case at the minute... 

 

Cheers, 

Alex
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Valued Contributor III
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Hi, Alex, thanks much for your reply. 

i read the open code, the ck/ck# is generated by altddio->altio_buf, it seems i can invert the signal, but as you said, it influence internal timing and quartus indeed gives timing violation warnings. i am now trying to find where i can invert clock safely, but you know it is not easy. 

 

As the option in board setting you advised, i think that cannot solve my problem, for addr/ctrl/cmd routing are all ok, just ck/ck# is swapped, i think the 'Maximum CK delay to DIMM/device' indicates ck/addr/ctrl/cmd as a group, well, i will try this option to see what happens. 

 

For we have added external series resisters for clocks, so we can debug our board cross soldering the resisters. 

however, i do interested in solving this problem in the fpga logic.  

there is an option 'addtional ck/ck# phase' in wizard, which i think could solve the problem, but unfortunately it is grayed. 

en, if altera guru knows how to fix it, please kindly help. 

 

Life is hard, we are working hard on it. 

 

Best Wishes, 

ingdxdy
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