DDR3 simulation for ArriaVSX

[Altera_Forum]

hello there. 

 I have a question.  I am simulating DDR3 IP-core.  I found README.txt in "*example_design/simulation" directory.  I tried to simulate IP core and example design according to what it says.  execute tcl file from Quartus Prime. and execute run.do file in ModelSim. that was fine, it is simulated of course.  but this is not what I want as you know.  I build my own project and simulated the whole project. it gives errors. message tells me something like this. error: module parameter \'cfg_cmd_gen_output_reg\' not found for override at alt_mem_ddrx_controller.v  I found solution. the libraries for DDR3-UniPHY must be listed fast  I found modelsim's macro here "simulation/modelsim/*run_msim_rtl_verilog.do". and modified it as I am told.  that works fine.  my question is. if so, why the library is not listed there automatically? the macro file is published by QuartusPrime. I think I will modify testbench again. I don't want to edit the macro each time.  do you have any idea?

[Altera_Forum]

Hello akira, 

 you are right the testbench created by Quartus is not suitable for simulation of custom hardware. I changed two verilog files to adapt the DDR3 model to my project. (ddr3_1_example_sim.v in ...\ddr3_1_example_design\simulation\verilog\ and ddr3_1_example_sim_e0.v in ..\ddr3_1_example_design\simulation\verilog\submodules\) Than I take a copy of the msim_setup.tcl (..\ddr3_1_example_design\simulation\verilog\mentor\) and extend it to compile my sources including the toplevel of my testbench. Renaming the 3 files will prevent overriding when generating the DDR3 sim model.  Jens

[Altera_Forum]

hy thanks Jens. 

well, it is bad. I want them to fix the problem.