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Honored Contributor I
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I'm implementing a Math Equation on my FPGA, am I following the right methodology?

Dear friends, 

 

This is my first project ever in FPGA. 

 

I'm implementing a Math Equation over a list of numbers (data) which range from 0 - 255, one by one, data can contain 100 or 10.000 or 50.000 numbers, it's irrelevant, it's also irrelevant the nature of the equation itself. 

 

I have finished a logic implementation in verilog in ModelSim-Quartus II, which can successfully load the values from a (simulated) memory and output the correct result after some iterations.  

 

Now I wish to implement it in "real life" on my board DE1-SOC. The first thing I need to do is to "fill" the memory on the FPGA board with the data to process, data comes from my PC, once it's filled, I want my logic to start to process the data and output the results, outputting values back to the memory. 

 

From here the board should make a little choice regarding a threshold of the resulting data and to produce 3 groups from here. The way the board do that isn't of my concern, since my task is only to design the logic implementation of the equation (which I already did). 

 

Finally, system should send these 3 groups of data to my PC. 

 

 

I have some assumptions on how to do this. I wish to know your opinion and advice. I wish to know where to start and what tutorials to address and topics to study. 

 

I think this is the way to do it. This is SoC system and I have to start by implementing a QSYS project, with the convenient QSYS tool, matching the components, the IO ports Jtag-UART, the on-chip memory, my logic implementation and finally the NIOS-II implementation. 

 

Nios-II would control the entire board function from loading the data into the memory, then activating the designed logic unit and waiting until it finish, then making the little threshold grouping and send it back to my PC. 

 

Ok, with all the above, is this correct? Should I go ahead and search more information under this method?Is this the simplest way to do it?
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Honored Contributor I
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That is one way to do it. But can you load any data you want into the memory without re-compiling the system? 

Another method would be to load the data serially from a PC, maybe via UART? then you could process as much real time data as you wanted.
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Honored Contributor I
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--- Quote Start ---  

That is one way to do it. But can you load any data you want into the memory without re-compiling the system? 

Another method would be to load the data serially from a PC, maybe via UART? then you could process as much real time data as you wanted. 

--- Quote End ---  

 

 

I want to thank you Tricky for your patience, so what do you mean by "without re-compiling the system"? One observation is that I should be able to load different sets of data (different photos, same resolution, same characteristics), so I guess you mean that, I wish to be able to analyze different set of datas. 

 

That method that you mention, how to do this? any specific tool to use? wouldn't be that a Qsys sytem also? Is the ARM play any part on this?
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Honored Contributor I
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Because it is a SOC, much of the DE1-SOC material centers around getting the ARM HPS running Linux etc. If you are comfortable with that (software background?) you would benefit from getting your board up and running to that point. While you can have a NIOS-II, I would not suggest that unless you are not comfortable at all with the ARM+Linux approach usually used on that board. 

 

Without knowing anything about your algorithm or background, a kind of "natural" system would be one where your Linux application software takes care of all of the PC data transfer and populating buffers in memory. 

 

The first generation of your Qsys component for your math block could simply implement an Avalon-MM control port, where one control register receives the data one-write-at-a-time and another control register is where the result is posted. 

 

If your goal is to avoid software at all costs and focus on the HDL development of your math block, I would suggest just using an Avalon-MM control port in your component, and then using the JTAG-Avalon-MM Master component along with system-console on your PC to do your read/writes and maybe TCL script.
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Highlighted
Honored Contributor I
2 Views

 

--- Quote Start ---  

I want to thank you Tricky for your patience, so what do you mean by "without re-compiling the system"? One observation is that I should be able to load different sets of data (different photos, same resolution, same characteristics), so I guess you mean that, I wish to be able to analyze different set of datas. 

 

That method that you mention, how to do this? any specific tool to use? wouldn't be that a Qsys sytem also? Is the ARM play any part on this? 

--- Quote End ---  

 

 

This all depends on what you're doing. Assuming you're using purely FPGA approach, you need to get data into it somehow. The quickest but probably "dirtiest" is to have a ROM in your design initialised with all the values you need - but obviously you're limited to the data in the rom and changing that data requires re-compiling the design. 

 

The better (and only real useful method) is to connect it via some connection so that data can be sent to the design somehow. This may be directly via a UART, PCIe, Ethernet etc. Or via some shared ram space if you're part of some SoC system.
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