mSGDMA: stream-to-memory setup problem

[Altera_Forum]

Hi all, 

 I am trying to set up a stream-to-memory system using the mSGDMA. I'm using Quartus 13.0.  My streaming data path consists of the following (see st_to_mm_mSGDMA_Qsys attachment):  Test pattern generator (YCbCr 4:2:2) -> Avalon-ST Timing Adapter -> mSGDMA write master   The mSGDMA write master is controlled by a mSGDMA dispatcher.  The slave ports on the dispatcher are all connected to the data_master line of a NIOS II processor, and the master line of the write_master is connected to the slave port of the DDR2 SDRAM Controller with ALTMEMPHY.  The the code which I'm using to run the mSGDMA components is attached (st_to_mm_TestCode.txt)  The output from my code is the following:  CSR Status reg: 0xFFFFFFFF read_busy() = 1 read_csr_write_descriptor_buffer_fill_level() = 65535 Waiting for descriptor buffer to empty  And the code stays in the while-loop calling "read_descriptor_buffer_full()", since the buffer seems to always be full.  So my questions are: 1) Why would the CSR status register return 0xFFFFFFFF? Why would the descriptor buffer be full? 1a) Would this occur if the modules were constantly being reset? i.e. wrong polarity of reset being used? What is the polarity of reset expected of these modules? 2) With respect to the Linker Script tab inside the NIOS II BSP Editor (See attachment), is it necessary to limit the size of the DDR2 available to the NIOS II default memory sections? i.e. would it be a good idea to say change the size of memory_ddr2 from 134217896 to half that size (67108864). 3) Does anyone have sample code for st-to-mm transfers using mSGDMA? I found a link here (http://www.alteraforum.com/forum/showthread.php?t=30273&page=2), but the code isn't accessible.  Thanks in advance for any help.