matrix array in vhdl

[Altera_Forum]

Dear all, 

 I have 4x4 matrix and I want to read this matrix row by row on each clock cycle. For example, row1 is read in cycle1, row2 is read in cycle2 and so on. Can anyone give idea how to write this code? Many thanks

[Altera_Forum]

Dear FvM, 

 "better use signed or unsigned types for the top entitie's port", can you explain on this? Thanks for reply.

[Altera_Forum]

when trying to compile it, it needs to map each bit to a pin. You need 5185 pins, which are not available. Because you have chosen to use integer, and not limit the size of the integer, each value is 32 bits. You could change this to 8 bits to divide the number of pins required by 4, but this is still too many. 

 Is this just a temporary solution, or do you expect to actually send the data for this matrix from somewhere? you would neve send an entire matrix like this to an FPGA from a CPU - a CPU simply does not have 5000 IO pins. You'd usually send it via some other transport mechanism.   So, the options you have: 1. Reduce the scope of integer to fewer bits. You can do this by saying:  type matrix_t is array(0 to 8, 0 to 8) of integer range 0 to 255; --8 bits per integer  2. Specify that all IO pins are virtual via the assignments editor. This is just a temporary solution to allow you to compile the design. It is not a final solution.  3. Install some other mechanism to transport the data into your FPGA that will fit.  And finally - Please Please Please go and read up about digital design.