need help in correcting errors in fifo verilog

Altera_Forum · ‎05-28-2011

Can u help me debug errors in the fifo code?

I am trying to find error but I have not suceeded in finding any.

module newfifo(rst,

clk,

din,

wr_in, //write_enable signal

rd_in, // read_enable

dout, //data_out

empty,//data_in

full);

input rst,

clk;

input [7:0]din;

input wr_in,rd_in;

output [7:0]dout;

output empty,full;

reg [7:0] dout;

reg [3:0]read_ptr, write_ptr; //read and write pointers

reg [7:0] mem [14:0];

always@(posedge clk or negedge rst)

begin

if (rst)

write_ptr<=0;

else if (wr_in==1)

begin

mem[write_ptr[3:0]]<=din;

write_ptr <= write_ptr+1;

end

always@(posedge clk or negedge rst)

begin

if (rst)

begin

read_ptr<=0;

dout<=0;

end

else if (rd_in==1)

begin

dout<=mem[read_ptr[3:0]];

read_ptr <= read_ptr+1;

end

endmodule

//testbench

`timescale 1ns / 1ps

module newfifotestbench();

reg rst;

reg clk;

reg [7:0] din;

reg wr_in;

reg rd_in;

wire [7:0] dout;

wire empty;

wire full;

newfifo h1 (.rst(rst),

.clk(clk),

.din(din),

.wr_in(wr_in),

.rd_in(rd_in),

.dout(dout),

.empty(empty),

.full(full));

/*

initial begin

$shm_open("newfifo.shm");

$shm_probe(clk);

$shm_probe(rst,din,dout,wr_in,rd_in,full,empty);

end*/

integer i;

always# 10 clk=~clk;

initial

begin

clk=0;

rst=0;

# 100 rst=1;

wr_in=1;

rd_in=0;

for(i=0;i<5;i=i+1)

begin

# 20 din[7:0]=8'b10101010;

# 20 din[7:0]=8'b11001100;

# 20 din[7:0]=8'b11111111;

end

wr_in=0;

rd_in=1;

# 1000;

end

endmodule

The problems that I am facing are:

dout signal always stays at 0000000 inspite of my read_en going high.

Secondly, can u give me tips on how to write statement for empty and full.

Kindly excuse me if there are any mistakes as I am a beginner.

Thanks in advance.

As I am not able to post my siumlation output as an attachment,as I do not have 5 posts till now, kindly visit this link h**p://images.elektroda.net/92_1306588874.png for the simulation image.

Altera_Forum · ‎05-28-2011

Check the sense of your reset.

Altera_Forum · ‎05-28-2011

I am sorry, I have not understood. do i need to check reset in my program? (reset is an asynchronous active low signal in my case.) can u explain in a slightly detailed manner?

Altera_Forum · ‎05-28-2011

Your code is active on low reset but your testbench raises reset so your design stays under reset. You need to release the reset by lowering it to '0'

Altera_Forum · ‎05-28-2011

oops!! i just understood the mistake now..thanks a lot!! but now,i realise that there are a few errors like immediately after my data_in is over, for a certain period of time although my rd_in is high, i don get dout immediately. its like there is an xxxxxxx state for one clock pulse before my dout starts. can u give me some tips on how to change so that i get my dout immediately after my din stops?

Altera_Forum · ‎05-28-2011

you will get one clock delay from address sampling point at least since sampling is at clock edge e.g. when address = 0 then it is read as zero at incoming clock edge and data0 becomes available at next clock edge.

With regards to x states this is trivial, you can just initilise your array mem but is not essential.