sir my following code gives null output:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tskw is
Port ( reset : in STD_LOGIC;
p : in STD_LOGIC_vector(2 downto 0);
q : out STD_LOGIC_vector(2 downto 0));
end tskw;
architecture Behavioral of tskw is
signal k: STD_LOGIC_vector(2 downto 0);
begin
process (reset)
begin
if (reset ='1') then
k <=p;
q<=k;
elsif (reset ='0') then
q<="000";
end if;
end process;
end Behavioral;
but during synthesis,there is no error. plz help.:cry:
