Ambiguity with CR3-store/load exiting settings

[Eugene_K_2]

I have Intel(R) Core(TM) i5-2500 CPU. RDMSR on IA32_VMX_PROCBASED_CTLS MSR gives allowed-0 settings 0x0401E172, allowed-1 settings 0xFFF9FFFE. This means bits 15 (CR3-load exiting) and 16 (CR3-store exiting) of Primary Processor-Based VM-Execution Controls must be 1. However I can set them to zero and no any invalid VM entries happen. Why?

CPU details:

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 42
model name      : Intel(R) Core(TM) i5-2500 CPU @ 3.30GHz
stepping        : 7
microcode       : 0x26
cpu MHz         : 1600.000
cache size      : 6144 KB
physical id     : 0
siblings        : 4
core id         : 0
cpu cores       : 4
apicid          : 0
initial apicid  : 0
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx lahf_lm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid
bogomips        : 6600.13
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:

[Eugene_K_2]

Got the reason. I should have checked IA32_VMX_TRUE_PROCBASED_CTLS MSR instead of IA32_VMX_PROCBASED_CTLS because bit 55 of the IA32_VMX_BASIC MSR is read as 1.

[Quoc-Thai_L_Intel]

Thank you Eugene for providing the solution back to the communitiy!

The system programming guide has more details on the Intel(R) virtual-machine extensions: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf

Regards,
Thai