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Is there a link to the current/latest revision for the subject document?
Enio.
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Hello,
Thank you for posting your question on the Intel Software Network forum. This discussion forum is used primarily for software discussions. Can you tell me what this applicate note 485 relates to?
Best regards,
Jim A
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App Note 485, titled "Intel Processor Identification and the CPUID Instruction", contains the details on how to programmatically identify an Intel processor. The latest revision I could find was rev. 30 dated January 2006. There have already been processor changes to that are not reflected in rev. 30,but I can't find a newer one, although is possible it hasn't been updated yet.
The reason I asked is that using the "search" feature always returns many links to AP-485 documents that are old. Using the Core Duo processor as an example (http://developer.intel.com/design/mobile/core/duodocumentation.htm) it would be very helpful if, along with the links to the manuals, a link to the latest revision of AP-485 were included.
Thanks,
Enio.
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I'm with eniopineday andwould also like to know where there's an authoritative copy of app note 485. That app note seems to havebeen very poorly maintained, requiring developers to spend their time reading through each of the hardware specification updates to find out simple things like what signatures each processor returns.
It's been over a month sine eniopineday's posting and there's no reply here from Intel. Same for previous (very old) requests for this info from Intel.
What's going on?
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Hi,
Very sorry for the delay - we are stilllooking into this for you. We'll let you know as soon as we have more information.
Lexi S.
IntelSoftware NetworkSupport
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Hi,
Very sorry for the delay - we are stilllooking into this for you. We'll let you know as soon as we have more information.
Lexi S.
IntelSoftware NetworkSupport
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The owners of this appnote tell us that an update is in the works. We'll post more info as we have it.
==
Lexi S.
IntelSoftware NetworkSupport
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September 2006 revision is up: http://developer.intel.com/design/xeon/applnots/241618.htm
==
Lexi S.
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Hi there,
Seems that the AP-485 September 2006 has a errata in page 29. In the table 3-7 of Cache Descriptor Decoded Values. There are two values (56h, and 57h) with the same descriptor; and even if it is a vilid redundancy, at least a CPU, the Intel Core 2 Duo T7400 2.16Ghz, gives both descriptors at the same time...
So which is the wrong description and what should it be?
Regards.
David.
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The owners tell us thishas been confirmed as a documentation issue which will be corrected in revision -032.
Reference: AP-485 Intel Processor Identification and CPUID Instruction, September 2006
Document Number: 241618-031
Pg 29 Table 3-7. Descriptor Decode Values
|
Value |
Cache or TLB Description |
|
56h |
L0 Data TLB: 4 MB pages, 4-way set associative, 16 entries |
|
57h |
L0 Data TLB: 4 MB pages, 4-way set associative, 16 entries |
Revised
Pg 29 Table 3-7. Descriptor Decode Values
|
Value |
Cache or TLB Description |
|
56h |
L0 Data TLB: 4 MB pages, 4-way set associative, 16 entries |
|
57h |
L0 Data TLB: 4 KB pages, 4-way set associative, 16 entries |
==
Lexi S.
IntelSoftware NetworkSupport
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I must add that it really sucks when descriptor 0x49 means two different things depending on the CPU family and model.
What is even worse is that the family and model numbers mentioned in AP-485 alone (0xF and 0x6) are not enough to identify Xeon MP chip because 0xF and 0x6 can be Presler as well.
I find the lack of clear explanation of how to properly differentiate between CPUs with the same family and model number quite disturbing.
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True, Presler and Dempsey are family 0Fh and model 06h,however neither of them have an L3 cache. The Tulsa processor is the Intel Xeon MP processor that is family 0Fh, model 06h and can have an L3 which reports this descriptor.
The BIOS industry has to determine MP vs. DP processors. One of the methodsBIOS uses is to interrogate CPUID function 80000008h. If 40 is returned as the physical address size, then the processor CPUID executed on is an Intel Xeon MP processor.
Another method of determining cache level information is to execute CPUID function 4 with ECX incrementing from 0 to N until EAX[4:0] == 0. During one of the itterations if EAX[4:0] == 3 then you have an L3 and the 49h descriptor refers to a 3rd level cache.
Yet another method is to parse the cache descriptors returned by CPUID function 2. If you get different a cache descriptor other than 49h that also refers to the L2, then the 49h refers to the L3.
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Hi Igor,
We checked with the doc owners to be sure, and rev-031 (Sept. 2006) is still the newest. The location of the most recent version of AP-485 will remain here.
==
Lexi S.
IntelSoftware NetworkSupport
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Lexi, parts of the new AP-485 document revision (regarding the detection of SSE4.1, SSE4.2 and POPCNT as well as some other features of next generation CPUs) have leaked into the "Intel SSE4 Programming Reference" which is part of the "SDK for Intel 45nm Next Generation Core 2 Processor Family and Intel SSE4".
I am sure that info came from AP-485 because I recognize the format (they probably simply copy/pasted the content). IMO, new fixed AP-485 revision should be put online ASAP because there were some errors in cache descriptor table both in previous version of AP-485 and in this new SSE4 reference manual.
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After several talks with the different document owners, we learned that although theformat is similar both to this appnote and to theIntel 64 and IA-32 Architectures Software Developer's Manuals,this SSE4 info actuallyisn't from any pre-release version of AP-485, which is notdesigned to include that type of information. One of the owners of the SDMs told us:
In general, much of the detailed information of pre-release processors ispublished in updated public documentation, such as AP-485, only after that processor reaches product launch status. The rationaleis thatwhen the product is reaching the marketplace, the relevant product informationis made public.
New instruction set extensions documentation, such astheSSE4 programming reference, are exceptions to that product-launch gating rule. As compiler tools are reaching the software development community (the Intel C++ Compiler 10.0 supports SSE4, as does Microsofts Whistler* beta release), Intel also made the relevant programming interface details of SSE4 available.
Cache descriptor information is a legacy interface for software to query product-specific information. It is governed by the first set of rules. Intel advocates using CPUID leaf 4 to query details of the cache hierachy instead of relying on cache descriptors, because the query inferface of CPUID leaf 4 is forward-compatible to pre-release processor without requiring the software coder to maintain a hardcoded table (requiring frequent maintenance to add new cache descriptor values with each processor launch) to look up cache descriptor values of all Intel 64 and IA-32 processors.
==
Lexi S.
IntelSoftware NetworkSupport
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