Big real mode switching on Conroe/Wood Crest

[derickmoore]

I'm an option ROM developer writing boot code. My question relates to assembly language coding for the Protected Mode/Real Mode switching and clearing the pipe line cache.

I have working code that handles the cache for previous generations of Intel processors, but I have heard that Conroe and Wood Crest require a 'far jmp' to clear the cache. I will copy the working code into this message, an perhaps someone, from Intel maybe, will take mercy on me an edit it to make it work on the new processors.

;************************************************************************
;* On entry here, GDT_fword either points to the 4GB GDT, or the
;* GDTReal GDT that was saved upon entry.
;************************************************************************

movzx ebx,bx ;zero fill ebx
add eax,ebx ;add offset to segment = linear address
mov dword ptr GDT_fword+2, eax ;store GDT address in far word pointer
lgdt fword ptr GDT_fword ;Load global descriptor table address

mov bx,08h ;Load bx to point to GDT entry 1, 0 is dummy
cli ;Disable interrupts

mov eax,cr0 ;Switch to protected mode
or eax,1 ;by turning on proper bit
mov cr0,eax ;and putting it in CR0

jmp PROTECTION_ENABLED ;Clear execution pipe
PROTECTION_ENABLED:

; mov ds,bx ;with GDT entry 1 (4GB segment limit)
; mov es,bx ;with GDT entry 1 (4GB segment limit)
mov fs,bx&nbs p; ;with GDT entry 1 (4GB segment limit)
; mov gs,bx ;with GDT entry 1 (4GB segment limit)
and al,0FEh ;Switch back to real-mode without
mov cr0,eax ;resetting the CPU

jmp PROTECTION_DISABLED ;Clear executionpipe
PROTECTION_DISABLED:

sti ;Enable interrupts

When I recoded this to use a 'far jmp', the machine dies when the jump is executed. I don't know why, and I can't find a code example to learn from.

Derick

P.S. If anyone knows a better place to put this post, I would appreciate the redirection.

[Intel_Software_Netw1]

Hi Derick,

This is a fine place for your post. We're asking around among our desktop server contacts to find you an answer -- stay tuned.

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

[Intel_Software_Netw1]

Here's onesuggestionwe've received so far from our engineering contacts:

The 64-Bit Extension Technology Software Developers Guide, Volume 1 says:

1.6.3.2. ACTIVATING IA-32E MODE
Operating system should follow this general sequence to activate IA-32e mode:
1. Starting from page-enabled protected mode, disable paging by setting CR0.PG = 0. Use the MOV CR0 instruction to disable paging (must be located in an identity-mapped page).
2. Enable physical-address extensions by setting CR4.PAE = 1. Failure to enable PAE will result in a #GP fault when an attempt is made to enable IA-32e mode.
3. Load CR3 with the physical base address of the Level 4 page map table (PML4).
4. Enable IA-32e mode by setting IA32_EFER.LME = 1.
5. Enable paging by setting CR0.PG = 1. This causes the processor to set the LMA bit to 1. The MOV CR0 instruction that enables paging and the following instructions must be located in an identity-mapped page, until such time that a branch to non-identity mapped pages can be effected.

Is the code on an identity-mapped page?
==

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us