In case readers of this forum don't monitor the "Software Tuning, Performance Optimization, and Platform Monitoring" forum here, I wanted to provide a link to a topic that I just posted there pertaining to the mapping of core numbers and CHA numbers on Knights Landing to the physical layout on the die. This mapping information can be used in conjunction with the mesh traffic counters in the uncore to create visualizations of traffic on the die that correspond to the actual topology of the die (including disabled cores, etc), and may be useful for other purposes....
The post in the "Software Tuning, ..." forum is at: https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/777530
The presentation spends more time on mapping the Skylake Xeon than on the KNL, so there may be some questions on how I derived the layout on KNL from the measurements. If anyone is curious, please ask on the post linked above in the "Software Tuning, ..." forum so we can keep the discussion in a single forum thread.
