I am working on understanding the effect of prefetchers on user programs. On SandyBridge I could turn on/off prefetching by setting/resetting bits of MSR 0x1a4. However I could not find any documentation regarding the same for Knights Landing (KNL) architecture. So, I would like to know if is there a way by which hardware prefetching on KNL can be selectively turned on/off.
have you tried the way that worked for you on SandyBridge platform?
The same MSRs should work as it is a common part of the cpu.
0x1a4 MSR controls L1/L2 HWPs:
- 0x0 both enabled
- 0x3 both disabled
Hope it helps,
Thanks for the quick reply. I tried the same way as I was doing for SandyBridge and it worked. However, unlike SandyBridge where 4-bits are reserved for four prefetchers ( two for L1 and L2 each), on KNL only two bits are reserved for prefetchers one for L1 and L2 each.
I'm glad that it works for you Shilpa,
You are also right about the difference between Phi and regular Xeons.
Just in case you missed it here is more detailed explanation of HWP MSRs for regular Xeons: https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processo...