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Hi,
I'm using the Minnowboard Turbot. When debug info is enabled, by default, UEFI core prints log info to defaul serial console(0x3F8) in booting phase. I'm also trying to boot this UEFI image on my own custom board but there's no such serial port available. So my question is, is it possible to redirect these debug log to high speed UART1/2 in booting phase? I suppose this is controlled by the UEFI core code ? Is it configurable for user and how to? Big thanks.
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It's generated by the newest Intel Firmware Engine. The source project is Minnowboard-Max.
I tried to move the UART port and serial console from UART to HSUART0, but there is no debug log output from HSUART0. Thanks!
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First, let me know what version of firmware you are using.
Is this generated by Intel Firmware Engine, or is it one of the pre-compiled images from https://firmware.intel.com/projects/minnowboard-max ?
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It's generated by the newest Intel Firmware Engine. The source project is Minnowboard-Max.
I tried to move the UART port and serial console from UART to HSUART0, but there is no debug log output from HSUART0. Thanks!
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Did you also change the “Base address of the serial port registers” in the Settings menu under "Boot Settings" ?
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Dear LAURIE:
Do you mean the UART IRQ's address "0x3F8"? I don't know how to get the base address of HSUART0. I have tried the addresses such as 0x2F8,0x3E8,0x2E8, but it does't work.
I saw the Atom Processor E3800 Product Family Datasheet, but I did't find the SIO HSUART1's base address.
I can't get the port address of /dev/ttyS4 in linux too, it's 0x0000, even it can work.
# sudo serial -ag /dev/ttyS*
/dev/ttyS0, Line 0, UART: 16550A, Port: 0x03f8, IRQ: 4 Baud_base: 115200, ...
/dev/ttyS1, Line 1, UART: unknown, Port: 0x02f8, IRQ: 3 Baud_base: 115200, ...
...
/dev/ttyS2, Line 2, UART: unknown, Port: 0x03e8, IRQ: 4 Baud_base: 115200, ...
...
/dev/ttyS3, Line 3, UART: unknown, Port: 0x02e8, IRQ: 3 Baud_base: 115200, ...
/dev/ttyS4, Line 4, UART: 16550A, Port: 0x0000, IRQ: 39 Baud_base: 2764800, ...
/dev/ttyS5, Line 5, UART: 16550A, Port: 0x0000, IRQ: 40 Baud_base: 2764800, ...
...
Thank you.
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Hi,
It turns out that the HSUART(s) are MMIO Based. The MMIO address can be found by reading the MMIO bar in PCI configuration space (the MMIO bar is setup by PCI bus enum on the fly, not a static value) You can do a "PCI" command from the Shell prompt to see PCI configurations.
Unfortunately the Intel Firmware Engine this seems not to be configurable at this point since it assumes serial to be IO base and not selectable for MMIO but I will put in a ticket to add this.
In the Open source Minnowboard MAX code (firmware.intel.com/projects/minnowboard-max) this should be configurable by setting up the correct PCD values to check for if the serial port is MMIO or IO based.
Thanks,
Laurie
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I realize this post is very old, but...
I'm wondering if this is easily achievable now? If so, how. I want all serial UEFI I/O to occur on the first HS serial port.
Thanks
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