Knights Landing's MCDRAM Address Mapping

[proy4]

I am interested to know how MCDRAM address mapping happens in the Kinghts Landing. For a given physical address how it decides MCDRAM's row, column, bank, and channel? Is there any MCDRAM architecture spec that describes this procedure? Thanks in advance.

[Gregg_S_Intel]

It is something of a performance-testing-centric view.  Most customers would rather have a job finish, even if sub-optimally, than fail.  

For performance testing, better to check whether memory got allocated in a high-bandwidth node using hbw_verify_memory_region().