VMXON Help

[mjmonterey]

HI,

Hoping someone can help. I am working on getting an OS booted in VMM mode on an intel processor. I am using OWC 17 as the compiler. So far I have paging enabled and working. (32 bit mode with segmentation enabled). I checked the cpuid for the processor I am using and it does support VMX. I allocate a region in memory equal to size shown in IA32_VMX_BASIC_MSR (bits44:32) = 800 so I set it up as 2048 = 2k region size. I set the VMCS revision Identifier as shown in bits 31:0 of this msr = 13 (on my test processor). It is a 4k aligned region. My vmxon address is 66c000 (looks ok). Control Registers:

CR0 = 8001003b

CR4 = 2200

IA32_FEATURE_CONTROL MSR = 0xd

IA32_EFER.LMA = 0x0

EFLAGS = 246

A20 = 0x0

Then when I call vmxon I get interrupt 13 a GP - seems to not like my memory reference to the vmxon region?

Watcom does not have support for the Intel VMX instruction set so had to add lib with opcode for vmxon

unsigned long long vmxon_region;

void __near vmxon(void);

#pragma aux vmxon = \\

"nop" \\

"nop" \\

"push ebx" \\

"mov ebx, offset vmxon_region" \\

"nop" \\

"nop" \\

0xF3 0x0F 0xC7 0x33 \\

"nop" \\

"nop" \\

"pop ebx" \\

"nop" \\

"nop";

I assign the 32 bit addres to vmxon_region (a 64 bit long long) in another function and then call vmxon. I am not real clear about how vmxon works does it take indirect or direct address? Tried both and haven't gotten anything but GP

[David_O_Intel1]

I received this comment from an expert on the topic:

"VMXON requires that the address be a physical address. It looks like the address (assuming it is physical) meets the physical address width restrictions for VMXON on 32-bit processor (LMA==0)

One thing VMXON does require is that the VMCS revision identifier be written to the physical address provided as an argument to VMXON. The code fragmentabove does not initialize that. Maybethat is causing the GP?"

David Ott

[chrisadam]

The main entry point for using VMX is through the VMXON instruction. The instruction requires a single operand of a m64 region called the VMXON region. The memory region needs to be 4096-byte aligned (bits 0-11 must be 0) and the only VMCS field that should be modified is the VMCS revision identification field. This ID field should contain the value in bits 0-31 of MSR IA32_VMX_BASIC. In order to prepare a memory address in 32-bit PMode for use as an m64, some modifications need to be made. The upper 32-bits of the m64 on non long mode capable processors have to be 0 or an "invalid memory address" error will occur and a VMEXIT will be called.

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