What collateral/documentation do you want to see?

[BelindaLiviero]

Do you have questions that you are not finding the answers for in our documentation?  Need more training, source code examples, on what specifically?   Help us understand what's missing so that we can make sure we develop documentation you care about (what is important, and what is nice to have)!   Thank you

[Georg_V_]

I would hope to get better documentation on the exact semantics of the offload pragmas/declspecs/_Cilk*. For instance, _Cilk_shared on variables means that the value of the variable is shared, while _Cilk_shared on a function means that the code is compiled for host+accelerator. _Cilk shared am classes apparently means that all class methods are _Cilk_shared and the values of the members of each instance are shared - as long as they can be copied by binary copy.

The discussion of these in the compiler documentation and elsewhere is based on examples, rather than on a more formal description. Some issues where I still dont have a clear understanding: If a base class is declared as offload, what happens to derived classes? Under which circumstances will the compiler issue a warning "warning #2571: variable has not been declared with compatible "target" attribute" (and when is it important to listen to it)? In which cases will the compiler not emit such a warnung while in reality a target attribute would be necessary? ....

Just some things that currently bother me.

Georg

[Justin_Bennett]

We'd like to see some more specific hardware requirements for the host system.  We weren't aware that we would need a special motherboard/BIOS to support the card (due to our lack of research and hastiness :) so now we're trying to find out what the options are that will work for us.

Any information you have about what motherboard/BIOS features are necessary would be very helpful.

[BelindaLiviero]

@Greg:  thank you -- now looking for what you are asking

@Justin:  Does this link help at all? http://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-coprocessor-where-to-buy.html    If not, what information would be more helpful?    If this URL does the trick, then maybe we just need to make a more visible link to it from the mic-developer site......

[Justin_Bennett]

Belinda, 

I had actually seen that page in my searching, and it does help to some extent.  The problem right now is that I don't think many (if any) of those vendors are actually offering Xeon Phi solutions currently.

What would be more useful is a more generic list of BIOS/motherboard requirements so that we could look into putting a server together that would work.  It may be that the Intel boards listed on the Xeon Phi product page are the only ones that are currently compatible, but I don't know for sure if that's true.

[Dragos_Constantin]

Hi Justin,

If you have an empty PCI-E 2.0 x16 slot on your motherboard and the power supply has the right specs (XEON Phi 5110P needs 225W) you are in business.

Dragos

Justin Bennett wrote:

Belinda, 

I had actually seen that page in my searching, and it does help to some extent.  The problem right now is that I don't think many (if any) of those vendors are actually offering Xeon Phi solutions currently.

What would be more useful is a more generic list of BIOS/motherboard requirements so that we could look into putting a server together that would work.  It may be that the Intel boards listed on the Xeon Phi product page are the only ones that are currently compatible, but I don't know for sure if that's true.

[BelindaLiviero]

Justin: to add to what was said above,  the motherboard BIOS must support memory mapped I/O above 4GB (large Base Address Register support per the PCIe specification).

[Georg_V_]

Some additional suggestions where the current docs are not as useful as the could/should be:

• The documentation is particularly weak on C++ examples, and some important aspects such as vectorization of STL vectors, alignment of class data, Cilk Array Notation and STL are barely mentioned/considered.
• Organization of larger projects. For instance: Should I add "#pragma offload_attribute(push, target(mic))/pop" to my .h files (declarations), or should I better add it only to the .cpp files (implementation/definition). What about templates (usually need definition in .h)?
• How to handle cases where icc wrongly believes it has to compile for offload (internally doing 2 compiler runs), but where the mic side of the compile fails due to missing .h files (e.g. Qt files).

Georg

[Loc_N_Intel]

Hi Georg,

We appreciate your feedback. However, we don't totally understand your third concern: How to handle cases where icc wrongly believes it has to compile for offload (internally doing 2 compiler runs), but where the mic side of the compiler fails due to missing .h files (e.g. Qt files).

Would you like to elaborate your concern please? Thank you.

[kankamuso]

Hi,

I am having problems configuring the card. I get 3d and 3E post codes on dmesg duting card initialization and would like to find information about such codes and their meaning. I have posted a support request and some messages on the forum about the issue but no response yet :-(.If there is a problem with the card, I must know as soon as possible to return it...

Thanks in advance,

Jose

[Kevin_D_Intel]

I can't speak to what might be the issue with the card but post codes are available in the MPSS readme (here: http://software.intel.com/en-us/articles/intel-manycore-platform-software-stack-mpss) that may help with their meaning.

What is your Premier issue #?  (I will ping the HW support side)

[kankamuso]

Kevin Davis (Intel) wrote:

I can't speak to what might be the issue with the card but post codes are available in the MPSS readme (here: http://software.intel.com/en-us/articles/intel-manycore-platform-software-stack-mpss) that may help with their meaning.

What is your Premier issue #?  (I will ping the HW support side)

thanks for your response. I posted a support issue but just received an ack mail without any issue #. By the way, I am also unable to find the post codes on the multiple files that are located under the downloading page you provide.

best regards,

Jose

[Kevin_D_Intel]

Hi Jose. I'm very sorry for the goose chase. I did not realize the readme files for the public MPSS release were different than internally available versions.

If you purchased through an OEM then please contact them regarding the problem you described w/the card in your other thread. If not then let me know and I'll see how I can help.

[Georg_V_]

loc-nguyen (Intel) wrote:

We appreciate your feedback. However, we don't totally understand your third concern: How to handle cases where icc wrongly believes it has to compile for offload (internally doing 2 compiler runs), but where the mic side of the compiler fails due to missing .h files (e.g. Qt files).

Would you like to elaborate your concern please? Thank you.

Apparently, icc launches the MIC-side of the compiler if it finds something like a "pragma _offload", "_Cilk_shared", attribute etc. somewhere in the sources that it compiles for the host. If I add those annotations to header .h files, this will trigger MIC-compilation for all  .cpp files that include one of those headers - even if the actual code (.cpp) does not have a single place where MIC is called.

I found this compiler behaviour quite annoying (it may be suitable for small projects). In particular, in C++ you sometimes have to put those annotations into headers, e.g. for header-only implementations or templates. Also, the compiler will complain about methods/classes not available for offload if an offloaded method accesses a class that has not been declared offload (and declaration usually happens in the .h file...).  Plus there are cases where the compiler wrongly assumes that an offload version of a method is required (I opened a Premier issue for this). Unfortunately, adding attributes to headers was the first approach I took, and it failed miserably. This is a kind of catch-22....

I the end, I changed my makefiles to add "-no-offload"/"-offload-attribute-target=mic" options to the makefiles-only very few changes to .cpp and .h files.

Georg

[David_B_16]

Belinda,

I've been looking for the source code for the black-Scholes and Monte Carlo european options case studies. As I would like to compile and run the codes for a learning exercise on how to use the MIC architecture. I think it would be a good idea to have some example codes available to download and play with, to get a hands on feel for programming on the Xeon Phi.

David

[Kevin_D_Intel]

kankamuso wrote:

Quote:

Kevin Davis (Intel)wrote:

I can't speak to what might be the issue with the card but post codes are available in the MPSS readme (here: http://software.intel.com/en-us/articles/intel-manycore-platform-software-stack-mpss) that may help with their meaning.

What is your Premier issue #?  (I will ping the HW support side)

thanks for your response. I posted a support issue but just received an ack mail without any issue #. By the way, I am also unable to find the post codes on the multiple files that are located under the downloading page you provide.

best regards,

Jose

Jose - FYI - the readme files for the new MPSS Gold Update 2 (posted 3/7/2013) now include the post codes.

[Bruce_Weaver]

Hi,

Speaking for a large set of the scientific community, I'd like to see more Fortran examples.  Let's face it, we all learn best by example; detailed documentation is pretty much only useful after you have a pretty good idea of what you're doing.  One of the attractions of the PHI is not having to get too close to the metal (we gave up on converting our code to a GPU) and Intel has been using that compatibility to sell the concept of the PHI.  Most scientific code is constantly changing and we scientists would like to do more science and less programming.  Fortran is more accomodating to heavy computer users who don't want to be full-time coders.  Some disciplines use it more than others but there are a lot of HPC folks, like my small group, who are using several hundred CPU hours/week and are moving up to several thousand/week. Some of my Fortran-touting colleagues use hundreds of times that. 

thanks,

[Frances_R_Intel]

Bruce Weaver wrote:

Hi,

Speaking for a large set of the scientific community, I'd like to see more Fortran examples. 

The advanced labs for the training videos, including Fortran versions, should be making it out to the web late this week or early next.  It's a start at least. Luckily Fortran is a good fit for the Intel(r) Xeon Phi(tm) coprocessor. But yes, we do need to put more Fortran out there.

[McCalpinJohn]

I would like to see two things:

(1) Documentation of the MSRs and/or PCI Configuration space registers used for the memory controller performance counters.  SEP/VTune provides a "memory bandwidth" measurement set, but I have not found out exactly how this is being measured.

(2) Documentation of the physical address to distributed tag directory hash.   This does not matter for bandwidth (since contiguous addresses are spread across all of the distributed tag directories), but it can be very helpful for choosing addresses to be used for synchronization variables.   I have measured a 3:1 variation in cache-to-cache intervention latency as a function of address when sharing a cache line between two (adjacent) cores (depending on the distance between the cores and the distributed tag directory for each cache line address).   Being able to determine this locality programmatically should allow for the implementation of significantly more effective synchronization constructs.

[j0e]

Hi, I would find it useful to see some examples that combine MPI processes with openMP (or similar) thread generation (and in Fortran).  On HPC clusters I've iused in the past, I just matched # of cores to # of processes, but it appears the Phi benifits from running fewer processes with many threads.  Perhaps some of these examples are out there already, as I've only just started looking.

Thanks!

[BelindaLiviero]

for those of you who asked for some fortran examples, please take a look at http://software.intel.com/mic-developer > Training under "Code Samples", we recently published some Fortran labs there.

if you are looking for other (and more specific) examples, let us know.   

Thank you all so far for the feedback, we are working down the list of requests and will use this thread to respond on where we are with what you asked