how is physical memory "seen" by cpu?

minwang · ‎10-12-2004

Suppose I have 16M physical memory in my system. Is it true that cpu accesses all the physical memory by putting 0x000000-0xffffff on its address bus? If it is true, does it mean the minimal memory requirement for DOS is 1M(because 640k-1M area is mandatory for mapping for various purposes)? And how does the mapping work?Is it something like when system power up, it reads BIOS into physical memory area reserved for BIOS mapping?

Thanks,

Message Edited by minwang on 10-12-2004 01:03 AM

Intel_Software_Netw1 · ‎10-20-2004

We will ask our Application Engineers to help provide an explanation, and will let you know how they respond. In the meantime, we recommend starting with the IA-32 Intel Architecture Software Developers Manuals, vol. 1: Basic Architecture (http://developer.intel.com/design/Pentium4/documentation.htm), specifically Chapter 3.3, Memory Organization.

Regards,

Lexi S.

IntelSoftware NetworkSupport

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Message Edited by intel.software.network.support on 12-02-2005 08:33 PM

Intel_Software_Netw1 · ‎10-20-2004

Can you tell us what processor and system configuration you are working with? This seems to go back to the days of the Intel 286 processor, if youareworking on issuessurroundingthe memory between 640K and 1M.

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

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Message Edited by intel.software.network.support on 12-01-2005 10:18 AM

minwang · ‎10-21-2004

I'm not working with a specific processor right now. I'm just curious how host bridge works since POST. Can you give me some detailed information how decoding logic of cpu address bus(host bridge) initializes since POST? How does a device on a specific bus know which address in physical space to decode? If I have 128M physical memory(0 - 8000000), is it mapped to 0-8000000 of physical space? Basically physical space a0000-bffff is mapping of video ram, how does system make use of a0000-bffff on physical memory chip?

I tried to search on GOOGLE but can't find anything useful.

Thanks

Intel_Software_Netw1 · ‎10-26-2004

Our engineering contact on the BIOS team responded as follows:

All memory transactions from the CPU are placed on the host bus to be consumed by some device. Potentially the CPU itself would decode a range such as the Local APIC range, and the transaction would be satisfied before needing to be placed on the external bus at all. If the CPU does not claim the transaction, then it must be sent out. In a typical Intel architecture, the transaction would next be decoded by the MCH or memory controller and be either claimed as an address that it owns, or determining based on decoders that the transaction is not owned and thus would be forwarded on to the next possible device in the chain. If the memory controller does not find the address to be within actual DRAM, then it looks to see if it falls within one of the I/O ranges owned by itself (ISA, EISA, VL, PCI, PCI-X, PCI-E). Depending upon how old the system is, the memory controller may directly decode PCI transactions, for example. If the MCH determines that the transaction does not belong to it, the transaction will be forwarded on down the chain to whatever I/O bridge(s) may be present in the system. This process of decoding for ownership / response or forwarding on if not owned repeats until the system has run out of potential agents.

The final outcome is either an agent claims the transaction and returns whatever data is present at the address, or no one claims the address and an abort occurs to the transaction, typically resulting if 0FFFFFFFFh data being returned. In the specific case thatyou mentionin this question, where the 0A0000h - 0BFFFFh space seems to be owned by two different devices (VGA frame buffer and system memory), the Intel architecture uses the SMI signal to clarify which device should satisfy the transaction. If no SMI asserted, then the transaction is ultimately passed over by the memory controller in favor of allowing a VGA controller (if present) to claim. If the SMI signal is asserted when the transaction is received by the memory controller, then the transaction will be forwarded to the DRAM unit for fetching the data from physical memory. Look up more details on SMI (system management interrupt) or SMRAM mode for a better understanding.

==

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

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Message Edited by intel.software.network.support on 12-01-2005 10:19 AM

chazzeromus · ‎08-15-2009

Quoting - minwang

I'm not working with a specific processor right now. I'm just curious how host bridge works since POST. Can you give me some detailed information how decoding logic of cpu address bus(host bridge) initializes since POST? How does a device on a specific bus know which address in physical space to decode? If I have 128M physical memory(0 - 8000000), is it mapped to 0-8000000 of physical space? Basically physical space a0000-bffff is mapping of video ram, how does system make use of a0000-bffff on physical memory chip?

I tried to search on GOOGLE but can't find anything useful.

Thanks

I think it depends on the chipset model to provide you a specific answer. Generally the host bridge maps out memory access for whom the processor is requesting, it determines what maps to physical memory and what maps to hardware(DMA and other interconnects through the southbridge). Video memory maybe handled by an exteranal controller on board or on card, which if it's onboard noawadays mapping is facilitated by the northbridge. Modern chipset architectures like QPI uses a chipset architecture with a single IOH that facilitates the north and south bridge, but in this case the memory controller isn't located in in the northbridge/IOH in architectures that utilize QPI.

chazzeromus · ‎08-15-2009

Quoting - chazzeromus

I think it depends on the chipset model to provide you a specific answer. Generally the host bridge maps out memory access for whom the processor is requesting, it determines what maps to physical memory and what maps to hardware(DMA and other interconnects through the southbridge). Video memory maybe handled by an exteranal controller on board or on card, which if it's onboard noawadays mapping is facilitated by the northbridge. Modern chipset architectures like QPI uses a chipset architecture with a single IOH that facilitates the north and south bridge, but in this case the memory controller isn't located in in the northbridge/IOH in architectures that utilize QPI.

Nevermind me. What the intel guy said :)