The description in Volume 2 "Instruction Set Reference" of the Intel Software Developer's Guide seems clear enough -- CLFLUSH takes a linear address as its argument and flushes the cache line containing that linear address from all levels of the memory hierarchy and from all caches in the system.
Inside the L1 cache, all aliased virtual to physical translations map to the same cache set (on current Intel processors) so there is no difference between evicting the linear address and the physical address. (This can be more complex with other processors.)
Outside of the L1 cache, all addresses used by the system are physical addresses, so it is the physical address that gets broadcast globally for eviction. If that cache line was loaded into a cache using a different virtual address, it will get evicted anyway, which may be unexpected. (Virtual address aliasing is frowned on for data, but it is heavily used for instructions in Address Space Layout Randomization.)
