Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
Announcements
FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.
1792 Discussions

Enabling LBR fails quitely

Maor_H_
Beginner
‎05-20-2016 02:29 AM
954 Views

Hey,

My code enables LBR by setting 0x1 to DEBUG_CTL MSR (0x1d9), and works properly on 1 PC and 1 Server i've checked so far.

I'm executing the same code on XEON E5-2620, but when i read the MSR after setting, it's still 0, and the LBR stack is empty... is there anything special i need to do to set the LBR flag for this kind of processor? (don't know if it matters, but it is a multi processor server).

Thanks.

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.