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The Xeon E7 processors use a buffer chip between the processor and the DIMMs. This buffer chip has two channels on the DIMM side and one interface on the processor side. Under some circumstances, the buffer-to-processor interface can run at 2x the frequency of the buffer-to-DIMM interface.
In this case the bandwidth comes from running the DIMMs at a slightly slower speed, which then allows the buffer-to-processor interface to run at the 2x rate. It looks like the bandwidth comes from:
- Buffer-to-processor: 4 channels *(2*1.6 GT/s) * 8 B = 102.4 GB/s
- Buffer-to-DIMM: 8 channels * 1.6 GT/s * 8B = 102.4 GB/s
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The Xeon E7 processors use a buffer chip between the processor and the DIMMs. This buffer chip has two channels on the DIMM side and one interface on the processor side. Under some circumstances, the buffer-to-processor interface can run at 2x the frequency of the buffer-to-DIMM interface.
In this case the bandwidth comes from running the DIMMs at a slightly slower speed, which then allows the buffer-to-processor interface to run at the 2x rate. It looks like the bandwidth comes from:
- Buffer-to-processor: 4 channels *(2*1.6 GT/s) * 8 B = 102.4 GB/s
- Buffer-to-DIMM: 8 channels * 1.6 GT/s * 8B = 102.4 GB/s
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Hi John,
Thanks, that explains it! Do you know if the existence of this memory buffer documented anywhere? It looks like if you know it exists, you can Google some presentations and articles discussing it, but haven't really seen it mentioned in Intel datasheets or the optimization manuals.
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Yes, I agree that the memory buffers are often not discussed as prominently as other features of the platform. The datasheet of the memory buffer C112 and C114 is located here: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/c112-c114-scalable-memory-buffer-datasheet.pdf
They are also listed on ark: http://ark.intel.com/products/series/99059/Intel-Scalable-Memory-Buffers

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