How the LOCK CMPXCHG make sure the operation is atomic?

Software Tuning, Performance Optimization & Platform Monitoring

Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

How the LOCK CMPXCHG make sure the operation is atomic?

478 Views

We known LOCK CMPXCHG keeping the operation atomic , my question is how it make sure the operation is atomic?what happens behind the sences?

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.