How to use rdpmc for reading non-architectural performance counters?

[LY]

Hi Everyone,

I am confused about how to use rdpmc instruction to read non-architectural events. For example, an event named CYCLE_ACTIVITY.STALLS_L2_PENDING with event number: A3H umask:05H, how to set ECX to read it? I know for the fixed-function performance counter, it is to set the 30th bit to be 1 and for others to be 0. But how to encode the specific event into ECX and read it through rdpmc instuction?

Thanks!

[McCalpinJohn]

The programming of the core performance counters is described in detail in Chapter 18 of Volume 3 of the Intel Architectures Software Developer's Manual.  

The counters are programmed by writing to various control and configuration MSRs.  All the MSRs you need to access and all the bit fields you need to program are described in Chapter 18 (except for the Event and Umask bits, which are described in Chapter 19).   You will also need to refer to Chapter 35 to find out how to map the MSR name to an MSR number on your particular processor. 

[LY]

Hi Dr. McCalpin,

Thanks for telling me that. I have read chapter 18 and parts of chapter 19.

After reading all those materials, I think rdpmc is just for reading events designated by ECX register and put the values into EDX:EAX. For the fixed-function performance counter, by setting the 30th bit of ECX to be 1, we could get three of them which are instructions, actual cycles, reference cycles. For others, the 30th bit of ECX needs to be set 0, but how to select a specific event to monitor is the problem.

I don’t know whether my understanding is correct. I think some events could be read directly with rdpmc since they are predefined and fixed and have dedicated registers (like ones above). But for other events, there are limited counting registers, then that is why wrmsr is needed to select and enable counting registers for different events. In other words, most of the events needs wrmsr combined with rdpcm/rdmsr to be selected, counted and read.. Is my understanding right?

John McCalpin wrote:

The programming of the core performance counters is described in detail in Chapter 18 of Volume 3 of the Intel Architectures Software Developer's Manual.  

The counters are programmed by writing to various control and configuration MSRs.  All the MSRs you need to access and all the bit fields you need to program are described in Chapter 18 (except for the Event and Umask bits, which are described in Chapter 19).   You will also need to refer to Chapter 35 to find out how to map the MSR name to an MSR number on your particular processor. 

[McCalpinJohn · Accepted solution]

It sounds like you are getting the "fixed function counters" and the "architectural performance counter events" confused.

The fixed-function counters are the only core performance counters that can be used without programming a performance counter event select register (using a PERFEVTSEL MSR).  The "fixed-function counters" each provide access to only one of the architectural performance counter events.  The fixed function counters can be accessed either by their "fixed-function MSR" or by using the RDPMC instruction with the counter number set to (1<<30), (1<<30)+1, or (1<<30)+2.

The remainder of the "architectural" performance counter events have nothing to do with the fixed function counters, and must be programmed in exactly the same way as the "non-architectural" events.  The difference with the "architectural" events is that they are expected to be carried forward to future systems.

[LY]

Thanks! I got it!

John McCalpin wrote:

It sounds like you are getting the "fixed function counters" and the "architectural performance counter events" confused.

The fixed-function counters are the only core performance counters that can be used without programming a performance counter event select register (using a PERFEVTSEL MSR).  The "fixed-function counters" each provide access to only one of the architectural performance counter events.  The fixed function counters can be accessed either by their "fixed-function MSR" or by using the RDPMC instruction with the counter number set to (1<<30), (1<<30)+1, or (1<<30)+2.

The remainder of the "architectural" performance counter events have nothing to do with the fixed function counters, and must be programmed in exactly the same way as the "non-architectural" events.  The difference with the "architectural" events is that they are expected to be carried forward to future systems.