Software Tuning, Performance Optimization & Platform Monitoring
Discussion around monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform monitoring
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IMC counters



I ran into this thread talking about memory controller performance counters.

I have two questions about this:

(1) These are also MSR registers. So there're per-core? 

(2) As shown in the VTune, these counter (e.g. UNC_M_RD_CAS_RANK0.BANK1) can show the detailed number of accesses to specific rank/bank. How many DIMMs connecting to one memory controller? Can the memory controller differentiate different  memory DIMMs?  

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Black Belt

The web page linked to above is only applicable to the 2nd, 3rd, 4th, 5th, and 6th generation Intel Core i3/i5/i7 processors.   (This also includes the Xeon E3 processors, but not the Xeon E5 or Xeon E7 processors.)

The interfaces described on that web page are not MSR counters, they are implemented in memory-mapped IO locations.   These are "per-package" counters -- they can be read by any core, but all cores read the same counters.


The VTune references to events with names like UNC_M_RD_CAS_RANK*.BANK* are only included in the files for the "IvyTown" (Xeon E7 v2) processors.   The uncore of the Xeon E7 v2 processors is completely different than the uncore on the Core (and Xeon E3) processors, so none of the documentation of one is applicable to the other.