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Intel PCM- Unsupported Processor Model error (Intel(R) Xeon(R) CPU E7-4860 v2 @ 2.60GHz (62))

Mahwish_A_
Beginner
458 Views

I am running PCM (version 2.8) numa and power utilities on Ivy Bridge platform (Intel(R) Xeon(R) CPU E7-4860 v2) Model 62 but getting this "Unsupported Processor Model" error. pcm-power reads returns my model number as -1.  Is it not supported by PCM v2.8?

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9 Replies
Roman_D_Intel
Employee
458 Views

Could you please post the entire output of pcm-power and pcm-numa?

Thank you,

Roman

Mahwish_A_
Beginner
458 Views

Roman

I get the following message for pcm-numa and pca-power respectively:

"pcm-numa tool does not support your processor currently."

"Unsupported processor model (-1)"

 

 

 

Mahwish_A_
Beginner
458 Views

I think the problem was because of NMI watchdog which was enabled. After disabling it, PCM now detects the model. 

Roman_D_Intel
Employee
458 Views

Thanks for you message. We will improve the error reporting in the next version of the code.

Mahwish_A_
Beginner
458 Views

As mentioned above, I am running pcm-numa.x on Ivy Bridge platform model 62 (Xeon E7 v2). PCM can detect my model number 62 but classifies it as IVYTOWN instead of IVY_BRIDGE due to the definition in enum SupportedCPUModels . I swapped the definition of IVY_BRIDGE and IVYTOWN in SupportedCPUModels  (IVY_BRIDGE=62, IVYTOWN =58) so that it that correctly identifies the architecture too. 

Now when pcm-numa.x calls initUncoreObjects() function, I get the following error: 

"Can not read memory controller counter information from PCI configuration space. Access to memory bandwidth counters is not possible.You must be root to access these SandyBridge/IvyBridge/Haswell counters in PCM."

I am not running pcm-numa.x with root access but I do have R/W access to MSR registers. Can you advise on this? 

Roman_D_Intel
Employee
458 Views

1) You should not change the CPU ID. The server processor (E7/E5 v2) with the Ivybridge uarchitecture had the codename IVYTOWN.

2) You need root access to access uncore memory counters.

Roman_D_Intel
Employee
458 Views

for 2) PCM accesses the root /dev/mem driver to program uncore PMU. Uncore PMU on Ivytown does not have msr interface.

Mahwish_A_
Beginner
458 Views

Is there a difference between offcore and uncore events? As I understand anything that any function which is not on the core is Uncore/Offcore e.g. L3/LLC  etc? However, Intel lists OFFCORE_RESPONSE_X and uncore events separately. Is it different to program an uncore event than an offcore? As given in pcm-numa.x, OFFCORE_RESPONSE_X for IvyTown is also programmed using event select registers and MSRs.

Roman_D_Intel
Employee
458 Views

The uncore and offcore response events are counted in different performance monitoring units (PMUs). The offcore response events are programmed in the core PMU.

pcm-numa uses the offcore response events, so the lack of access to the uncore PMUs should not result in an issue.

Best regards,

Roman

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