Intel PCM v2.9 - getting a list of supporting events

James_M_3 · ‎01-21-2016

I'm using Intel PCM V2.9 on an Ivy Bridge system. I want to use pcm-core.x to capture events of interest, but thus far am unable to get this working. For example, # pcm-core.x -e misalign_mem_ref.loads returns "Event 'misalign_mem_ref.loads" is not supported. This is the case for every event I try. The events are coming directly from the table in the Intel 64 IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. I am using the correct table for the Ivy Bridge chip. Questions: What is the desired syntax to specific events on the command line for pcm-core.x? How can I get a list of supported events from these tools?

Patrick_L_Intel · ‎01-21-2016

Hi James,

pcm-core.x uses Linux perf encoding syntax. It's probably easiest to first use ./pmu-query.py to search the events you're interested then copy the syntax to pcm-core.x to monitor specific core events.

Cheers,

Patrick

James_M_3 · ‎01-21-2016

Hi Patrick - Thanks for the response. I must be doing something wrong, and it likely has to do with the fact that I do not know the specific syntax pcm-core.x is looking for. I ran pcm-query.py which found misalign_mem_ref.loads, generating a description, cpu/mask value, event code and name. All good. I took the name provided and passed it as an argument to pcm-core.x, but I get the same error (output below). Please advise - again, I'm sure I'm simply using the wrong syntax on the command line, but nothing I have tried is working thus far. Thanks again - Jim Event to query (empty enter to quit):misalign_mem_ref.loads MISALIGN_MEM_REF.LOADS:Speculative cache line split load uops dispatched to L1 cache cpu/umask=0x01,event=0x05,name=MISALIGN_MEM_REF.LOADS/ Event to query (empty enter to quit): ... ./pcm-core.x -e MISALIGN_MEM_REF.LOADS Intel(r) Performance Counter Monitor: Core Monitoring Utility Copyright (c) 2009-2015 Intel Corporation Number of physical cores: 12 Number of logical cores: 24 Number of online logical cores: 24 ... 1: MISALIGN_MEM_REF.LOADS Event 'MISALIGN_MEM_REF.LOADS' is not supported. See the list of supported events Cleaning up

Patrick_L_Intel · ‎01-21-2016

Hi James,

This is the output from my system. Hope it helps.

root@ivt-patrick-perfmon:~/pcm# ./pmu-query.py
...
{'Family-model': 'GenuineIntel-6-3E', 'EventType': 'core', 'Version': 'V17', 'Filename': '/IVT/IvyTown_core_V17.json'}
{'Family-model': 'GenuineIntel-6-3E', 'EventType': 'offcore', 'Version': 'V17', 'Filename': '/IVT/IvyTown_matrix_V17.json'}
{'Family-model': 'GenuineIntel-6-3E', 'EventType': 'uncore', 'Version': 'V17', 'Filename': '/IVT/IvyTown_uncore_V17.json'}
Event to query (empty enter to quit):mem_ref
MISALIGN_MEM_REF.LOADS:Speculative cache line split load uops dispatched to L1 cache
cpu/umask=0x01,event=0x05,name=MISALIGN_MEM_REF.LOADS/
MISALIGN_MEM_REF.STORES:Speculative cache line split STA uops dispatched to L1 cache
cpu/umask=0x02,event=0x05,name=MISALIGN_MEM_REF.STORES/
Event to query (empty enter to quit):

root@ivt-patrick-perfmon:~/pcm# ./pcm-core.x -e cpu/umask=0x01,event=0x05,name=MISALIGN_MEM_REF.LOADS/
...
1: cpu
2: umask=0x01,event=0x05,name=MISALIGN_MEM_REF.LOADS

Detected Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz "Intel(r) microarchitecture codename Ivy Bridge-EP/EN/EX/Ivytown"
Update every 1 seconds
Time elapsed: 999 ms
Event0: MISALIGN_MEM_REF.LOADS (raw 0x430105)

Core | IPC | Instructions | Cycles | Event0 | Event1 | Event2 | Event3
   0   0.27        386 K     1408 K        71         0         0         0
   1   0.25        274 K     1112 K        58         0         0         0
   2   0.35        382 K     1097 K        37         0         0         0
   3   0.26        212 M      808 M       113         0         0         0
   4   0.23        327 K     1432 K       135         0         0         0
   5   0.21        128 K      600 K        58         0         0         0
   6   0.31        112 K      360 K        25         0         0         0
   7   0.30        205 K      678 K        60         0         0         0
   8   0.22        198 K      909 K        80         0         0         0
   9   0.25        176 K      700 K        58         0         0         0
10   0.23        163 K      719 K        81         0         0         0
11   0.34        100 K      297 K        26         0         0         0
12   0.34         71 K      210 K        15         0         0         0
13   0.40        125 K      317 K        17         0         0         0
14   0.29         79 K      274 K        26         0         0         0
15   0.34         71 K      210 K        15         0         0         0
16   1.04       4487 K     4320 K       409         0         0         0
17   0.32         95 K      299 K        26         0         0         0
18   0.32         99 K      312 K        26         0         0         0
19   0.22        199 K      904 K       103         0         0         0
-------------------------------------------------------------------------------------------------------------------
   *   0.27        219 M      824 M      1439         0         0         0

^CDEBUG: caught signal to interrupt (Interrupt).
Cleaning up
Zeroed PMU registers

Patrick

James_M_3 · ‎01-21-2016

Thank you Patrick. As I suspected, I was doing it wrong!

All the best

Jim

BHawk · ‎03-21-2017

Hi Patrick,

The pmu-query.py script is trying to access a url "https://download01.org", which is offline. Is there any other way to run this script?

I've had other Intel tools fail while looking for that site. It would be really great if your developers would stop using transitory domains. Why not just use Intel's domain? Or better yet, bundle the files. Developers are equipped for development, so it doesn't matter if the files are big. Thanks.

Byron

Patrick_L_Intel · ‎03-21-2017

Hi Byron,

I think you have a typo in the url. It's https://download.01.org You missed the '.' between download and 01.org. By the way, 01.org is also Intel's domain name and it hosts a bunch of Intel initiated open source projects.

Thanks,

Patrick

Zhuoran · ‎07-22-2019

Patrick Lu (Intel) wrote:
Hi James,
This is the output from my system. Hope it helps.
root@ivt-patrick-perfmon:~/pcm# ./pmu-query.py
...
{'Family-model': 'GenuineIntel-6-3E', 'EventType': 'core', 'Version': 'V17', 'Filename': '/IVT/IvyTown_core_V17.json'}
{'Family-model': 'GenuineIntel-6-3E', 'EventType': 'offcore', 'Version': 'V17', 'Filename': '/IVT/IvyTown_matrix_V17.json'}
{'Family-model': 'GenuineIntel-6-3E', 'EventType': 'uncore', 'Version': 'V17', 'Filename': '/IVT/IvyTown_uncore_V17.json'}
Event to query (empty enter to quit):mem_ref
MISALIGN_MEM_REF.LOADS:Speculative cache line split load uops dispatched to L1 cache
cpu/umask=0x01,event=0x05,name=MISALIGN_MEM_REF.LOADS/
MISALIGN_MEM_REF.STORES:Speculative cache line split STA uops dispatched to L1 cache
cpu/umask=0x02,event=0x05,name=MISALIGN_MEM_REF.STORES/
Event to query (empty enter to quit):
root@ivt-patrick-perfmon:~/pcm# ./pcm-core.x -e cpu/umask=0x01,event=0x05,name=MISALIGN_MEM_REF.LOADS/
...
1: cpu
2: umask=0x01,event=0x05,name=MISALIGN_MEM_REF.LOADS
Detected Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz "Intel(r) microarchitecture codename Ivy Bridge-EP/EN/EX/Ivytown"
Update every 1 seconds
Time elapsed: 999 ms
Event0: MISALIGN_MEM_REF.LOADS (raw 0x430105)
Core | IPC | Instructions | Cycles | Event0 | Event1 | Event2 | Event3
   0   0.27        386 K     1408 K        71         0         0         0
   1   0.25        274 K     1112 K        58         0         0         0
   2   0.35        382 K     1097 K        37         0         0         0
   3   0.26        212 M      808 M       113         0         0         0
   4   0.23        327 K     1432 K       135         0         0         0
   5   0.21        128 K      600 K        58         0         0         0
   6   0.31        112 K      360 K        25         0         0         0
   7   0.30        205 K      678 K        60         0         0         0
   8   0.22        198 K      909 K        80         0         0         0
   9   0.25        176 K      700 K        58         0         0         0
10   0.23        163 K      719 K        81         0         0         0
11   0.34        100 K      297 K        26         0         0         0
12   0.34         71 K      210 K        15         0         0         0
13   0.40        125 K      317 K        17         0         0         0
14   0.29         79 K      274 K        26         0         0         0
15   0.34         71 K      210 K        15         0         0         0
16   1.04       4487 K     4320 K       409         0         0         0
17   0.32         95 K      299 K        26         0         0         0
18   0.32         99 K      312 K        26         0         0         0
19   0.22        199 K      904 K       103         0         0         0
-------------------------------------------------------------------------------------------------------------------
   *   0.27        219 M      824 M      1439         0         0         0
^CDEBUG: caught signal to interrupt (Interrupt).
Cleaning up
Zeroed PMU registers
Patrick

Hello Patrick,

I tried to use pmu-query.py to check the support list but I got an error as

C:\projects\pcm\x64\Debug>python2 pmu-query.py
'"pcm-core.exe -c"' is not recognized as an internal or external command,
operable program or batch file.
no core event found for CPU, program abort...

So I use the follow link to check counter event num/unmask value

https://software.intel.com/sites/default/files/managed/7c/f1/253669-sdm-vol-3b.pdf

I would like to know where I was wrong by running that py file to check. Much appreciated!