- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The web page of Intel Performance Counter Monitor has been updated to include version 2.4.It includes the following changes:
- Support of memory bandwidth metrics on the 2nd, 3rd and 4th generation Intel® Core™ processors using integrated memory controller counters (Linux).
- Support of memory bandwidth metrics on additional server systems based on Intel® Xeon® E5 processors.
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I still get following QPI counter errors on our host with Intel Xeon E5-4620 (Sandy Bridge) using PCM 2.4. Our motherboard is Dell Power Edge R720. Does it suppose to be so or there is some other way to work around this? Thanks.
ERROR: QPI LL counter programming seems not to work. Q_P0_PCI_PMON_BOX_CTL=0xffffffff
Please see BIOS options to enable the export of performance monitoring devices (devices 8 and 9: function 2).
Could you tell me the exact hardware counters and fomulars to calculate the QPI bandwidth on Sandy Bridge EP processors? I knew from other document that UNC_GQ_DATA.FROM_QPI and UNC_GQ_DATA.TO_QPI may not suitable.
Thanks a lot!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
>>>QPI bandwidth on Sandy Bridge EP processors>>>
I have found the formula for bandwidth calculation: 3.2Ghz(signalling speed)*2bits/Hz*20bits(data width)*0.8*2(2 links)/8bits.
For calculating QPI bandwidth you can obtain QPI signalling speed by reading (Xeon E5-2600 Uncore Guide) QPI_RATE_STATUS register qpi_rate bitfield.You can proceed further by using the formula above.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I still get following QPI counter errors on our host with Intel Xeon E5-4620 (Sandy Bridge) using PCM 2.4. Our motherboard is Dell Power Edge R720. Does it suppose to be so or there is some other way to work around this?
For accessing PCI counters on Intel Xeon E5 processors, you need to enable the respective counters in the BIOS. Have you found such an option in your BIOS? If not you would need to get a new BIOS from Dell that provides this option.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
>>>If not you would need to get a new BIOS from Dell that provides this option>>>
Is BIOS vendor obligated by Intel to provide such a option?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Unfortunately not. It is completely up to the OEM if they provide this option in their BIOS if they see a customer need for it.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks Thomas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Could you please point me intel performance monitor for windows 8
---- Vinod Mopuri
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Vinod,
Go to https://software.intel.com/en-us/articles/intel-performance-counter-monitor
The table of contents has a 'License and Download' section.
Follow the links to accept the license and download the code. It works on windows 8.
Pat
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Vinod,
please note that Intel PCM is released as source code. The intention is to provide sample code for how to access the performance counters. If you want Windows 8 binaries, you will need to compile the sources.
Kind regards
Thomas
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Thomas,
I have compiled and used Intel PCM v2.9 on Windows Server 2012 R2, but I noticed that your Win7 MSR driver (in WinMSRDriver) incorrectly affinitized its thread to requested CPU: the code is broken for sparse KGROUPs or in cases where NUM nodes are not assigned to KGROUPs in consecutive fashion. The affinitizing code for IO_CTL_MSR_[READ\WRITE] should use the API KeGetProcessorNumberFromIndex() to convert the logical CPU to a PROCESSOR_NUMBER, which contains the group number and processor number i that group.
Thanks,
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Louis,
thanks for bringing this issue to our attention. We will fix it in a future release.
Best regards,
Roman


- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page