Invalidation of the cache from L1 cache

[realbencutting]

Suppose that a cache line with Variable X is simultaneously uploaded to L1d of CPU0 and L1d of CPU1. After changing the value of X from CPU0, when CPU1's L1d Cache Line is invalidated. Is it impossible for CPU1 to copy the variable X from CPU0's L1d cache if CPU0 has a cache line with X? And even if this is not the case, I want to know if there are cases where CPU0 brings in CPU1'

[McCalpinJohn]

The exact same question was answered on stackoverflow 4 days before the question was repeated here.

https://stackoverflow.com/questions/71067471/invalidation-of-the-cache-from-l1-cache/