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On a processor that supports L3 CAT (Cache Allocation Technology), assume I create two partitions (P1 and P2). However, I run the instruction "clflush" on an address which should reside in P1 but after switching from P1 to P2. Will "clflush" evict the cache-line in P1 or not?
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Hello AAhma10,
Thank you for contacting us about this concern.
Could you please so kind and provide us more details about the configuration that you are trying to accomplish?
On the other hand, I will double check the information and proceed with the next step in order to provide you the most accurate information.
Best regards,
Emeth O.
Intel Customer Support Technician.
Under Contract to Intel Corporation.
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Hey,
Thanks for the response!
I have a Core i7-8700 (12M L3 cache, 4.6GHz) processor that I am trying to accomplish this on.
Please let me know if you need more details.
Thanks!
Adil
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