I'm considering using memory type aliasing (with PAT) in order to map same IO memory region both as UC and WC (with different virtual/linear address). I'd like to do it because in some cases it's better to have strong ordering for it, and weak ordering in others.
Intel SDM it says that "... it is possible to have a single physical page mapped to two or more different linear addresses, each with different memory types. Intel does not support this practice because it may lead to undefined operations ...". Is it discouraged because the processor can have undefined behavior in this case, or because i can have memory consistency issues if i don't take care of ordering/consistency myself?
Here is my best guess. Intel would only say they supported something if they actually tested the configurations/operations and could guarantee the results. There is (probably) not much demand for 'memory defined with multiple address aliasing' and the testing required (probably) goes up exponentially. And you have to worry about a lot more corner cases, and testing on all the variations of the chips (mobile, laptop, desktop, server) and maybe on all the OEM vendors (Dell, Lenovo, etc) and maybe all the memory vendors, in all the memory configurations. I don't really know how many of these validation processes are done inside Intel or left to the OEMs or memory vendors but I'm just trying to give an idea of what it takes to say "we support using X in mode Y". It can be a ton of work and Intel and the OEMs have to prioritize their work according to customer demand.
From my own experience, many years ago, we tried using a 'multiple address aliasing' config on a system and we eventually had to abandon it. I forget why but it seems like the system would either crash or return corrupt memory due to some weird corner case.
Mapping a region as both UC and WC is probably the least dangerous aliasing combination possible, but there are likely to be surprises as well. One nasty example is that the WC memory type allows speculative reads, while the UC type does not. This can cause problems if the speculative read causes an unintended side effect.
The recommended approach for devices that have address regions with different ordering requirements is to map them to two different BARs, with different memory types for each BAR. Obviously this only works if the regions are mostly separated, since there are a limited number of MTRRs available for mapping the regions that you want to be treated with a non-default type.