Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

PCM energy counters seems too consistent with time



The energy value I got from PCM counters seems only depends on execution time, more time, more energy. I performed a test (result shown in attachment), which performs the same amount of work load, and varies the frequency. The higher frequency, execution time decreases, energy decreases as well, which is counter-intuitive, since energy grows cubic with frequency, but time decrease linearly with frequency. In principle, even if execution time decreases, the energy cost should be higher. The same happens when I use more cores, more cores lead to shorter execution time, but turn more cores from C6 state to C0 state. But still the energy curve follows strictly with time curves. The processor I used is Intel Xeon E2630L, the the code I use to extract energy is as follows, is there sth wrong in my code?


        PCM *m = PCM::getInstance();
        if(m->program() != PCM::Success) return EXIT_FAILURE;

        SystemCounterState before_sstate = getSystemCounterState();

        clock_gettime(CLOCK_MONOTONIC, &start);


        clock_gettime(CLOCK_MONOTONIC, &stop);
        SystemCounterState after_sstate = getSystemCounterState();

       printf("MEASURE: %f\n", getConsumedJoules(before_sstate, after_sstate));


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3 Replies

Hello Lu,

I'm not quite sure I understand the graphs but, in general, the RAPL core energy usage, for a given frequency, is going to be proportional to the non-halted clockticks at that frequency.

The energy MSR values aren't based on actually measuring the energy as far as I know. They are estimates of the energy. I'm not sure what factors are used for estimating the energy and the factors may change with different types of chips... and no, the factors are probably not going to be made public.

Does this help?


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Hi, Pat

Your information is quite useful to me. Thanks:)

Is there some figures shows how large the relative error can be in the worst case for the energy counters comparing measurements from power meter etc? If it is within a few percent, we can use it to support our research.

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Black Belt

You might want to try a broader set of test kernels, including kernels compiled with different ISA options (i.e., SSE vs AVX).

Assuming that your processor is a Xeon E5-2630L (Sandy Bridge), the Xeon E5 Family Specification Update (document 326510-014, August 2013) reports that the Package Energy Counter register may incorrectly report power consumed by AVX instructions (errata BT214).  The document does not disclose whether the error is in the undercounting or overcounting direction (or whether it can err in both directions), so trying a code that has been compiled for SSE may show different results.

One example of apparent success in using the energy counters is provided in a technical report from Berkeley (EECS-2012-168.pdf)
I have some issues with certain aspects of the methodology used, but the DGEMM results in Figure 2b show the expected increase in total energy use as frequency is increased.   The execution time goes down linearly with increasing frequency, but the power consumption increases faster than linearly with increasing frequency, leading to increased total energy use.

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