Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Performance event "Pin control (bit 19)"

Intel manual volume 3, In IA32_PERFEVTSELx MSR, there is a special event control bit:
PC (pin control) flag (bit 19) — When set, the logical processor toggles the PMi pins and increments the counter when performance-monitoring events occur; when clear, the processor toggles the PMi pins when the counter overflows. The toggling of a pin is defined as assertion of the pin for a single bus clock followed by deassertion.
I can't find any information what those PMi (note the small i) pins are. What can I do with them, where are they wired to? Thank you for your help.
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Black Belt

The answer will depend on the specific processor in question, as well as what the board manufacturer decided to do with that pin.

As an example, the document "Intel Xeon Processor E5-1600, E5-2600, and E5-2600 v3 Product Families Datasheet, Volume 1 of 2, Electrical" (Intel document 330783, revision 002, June 2015) talks about these pins in Section 4.7 in the section on JTAG and TAP signals.   The signals named "BPM_N[0:7]" are described as

Breakpoint and Performance Monitor Signals: I/O signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. These are 100 MHz signals.

If you need more detailed information, you will probably (but not certainly) need documents that are only available under NDA -- typically for OEMs who are making motherboards for these processors.

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