Regarding the STLB described in:Intel 64 and IA-32 Architectures Software Developers ManualVolume 3A: System Programming Guide, Part 1
Question: Is the DTLB (and ITLB) a subset of the STLB? Or does the STLB only contain evicted I/DTLB entries?
You pointed to the correct reference document. Figure 11.2 and table 11.1 contain descriptions of these structures.
Distinct or not, the original question is unanswered. The question as I understand it (and would like to ask) is:
If STLB is a secondary level TLB does it act effectively as a cache for the ITLB and DTLB? If this is the case, does the STLB act as an exclusive or inclusive cache of those TLB entries? I.e., when, say, a DTLB miss occurs and there is a hit in the STLB for the requested translation, does the STLB continue to hold the entry even after that entry is deposited by the TLB miss handler into the DTLB (thus effectively wasting the STLB entry since it is a duplicate of a lower level cache entry) or is that STLB entry marked as invalid so that it will immediately fill with the next TLB miss's translation?
Thanks for your careful consideration to this question.