Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Sandy Bridge RAPL energy counter overlap?

Black Belt

According to section 14.7 of Volume 3 of the Intel SW Developer's guide (325384-047) the RAPL infrastructure defines three "domains" on server platforms: Package, PP0, and DRAM.

Unfortunately, I am unable to parse the description of how these domains relate.  The text near the beginning of section 14.7 reads:

--- Begin quote ---
Generally, these RAPL domains may be viewed to include hierarchically:

  • Package domain is the processor die.
  • Memory domain include the directly-attached DRAM; additional power plane may constitutes a separate domain.

--- End Quote ---

I am trying to understand the overlap of these domains for energy consumption estimates, and the words above don't help at all!

It is fairly clear that the "Package" domain refers to the package, with energy consumption measurements summed over all the components (and power supplies) in the package.
It is fairly clear that "PP0" includes the processor cores, which probably (but not certainly) includes the private L1 and L2 caches.
It is fairly clear that the "DRAM" domain includes the directly attached DRAMs, but the comment "additional power plane may constitutes a separate domain" does not help at all....

So "PP0" is clearly a strict subset of "Package", but (Question 1) does any fraction of the "DRAM" domain overlap with the "Package" domain?

The reason I ask is that one of the six sets of power pins on the package matches the DDR3 voltage, so some power must be used in the chip at this voltage level.  I just can't tell whether it is counted in the "Package" domain or the "DRAM" domain, or whether it is small enough to be ignored.  (This last possibility seems unlikely -- the power consumed by the chip in driving the DDR3 data wires could easily be a couple of watts for a maximum-bandwidth store stream.  51.2 GB/s + ECC + commands comes out to ~512 Gbs, which requires 2.5 W at the fairly reasonably efficiency of 5 mW/Gbs (or 5 picoJoules/bit, if you prefer those units).  There might also be cases for which the memory controller might need to apply active termination to the DDR3 lines, and that could use power on the 1.5V line as well.)

Question 2:  Is there any way to tell if there are "additional power plane(s)" in the DRAM subsystem that would result in the "DRAM domain" not accounting for all of the energy use in the DRAMs?   I get non-zero numbers for energy consumption in this plane, but have not yet tried to correlate them with DRAM power models to see if they are in the expected range for the types of DRAM transactions that I am performing.

Thanks for any pointers!


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