Recently, I work on a E5-4603 chip. I was a little bit astonished by when I read related part of the chip in the official praogramming manual, because there is unexpectedly no event counter for SIMD integer operations, while many chips have, for exampe i7 chips, there is a event counter naming, SIMD_INT_128.PACKED_ARITH, event number 20H, Umask 12H.
Becasue in E5 chip description, the location of event number 20H, Umask 12H in E5 chip is empty, I guess maybe the event also functions in the Chip as well. I write a very simple benchmark, like:
int main ()
int i , j;
__m128i val = _mm_set_epi32(12,32,56,78);
for(i = 0; i < 10000; i++) //test with "i" in different order of number, 10, 100, 1000
val = _mm_sub_epi32(_mm_set1_epi32(0), val); //make invertion
//least significant 32bit passing
j = _mm_cvtsi128_si32 (val);
printf ("%d \n", j);
makefile (g++) looks:
CXXFLAGS = -msse4.1 -O3
all : main
r run : main
cl clean :
-rm -f main
perf stat -e r1220 ./main
I get expected raw value of the counter, proportionally increasing with the order of variable "i“ in benchmark.
My question is, is there any special intension or reason to mask this event in the technical manual for certain chips？
Accuately, I also test some other event. The results differ from events to events, i.e. some events are really not supported for certain chips, but some are just not listed in the manual.
The SIMD_INT_128 event is defined for sandybridge but was dropped from subsequent chips. It was not validated for sandybridge so I can't say if the counts are correct. Feel free to use the event but, if I were using the event, I'd probably try to code some sanity tests on the values before I relied on the result. The effort to validate events can take a lot of resources and, given that the event is not supported in ivybridge, the event was not validated and not added to the SDM.