Software Tuning, Performance Optimization & Platform Monitoring
Discussion around monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform monitoring

TLB Fault Processing and Caches

drMikeT
New Contributor I
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Hello,

referring to "xeons" (nehalem, Westmere, SB) operating in the Intel64 "IA-32e Protected" and "Paging" mode (full 64-bit support, see http://download.intel.com/products/processor/manual/325384.pdf Vol3A) data in the "Memory Management" data structures (p2-8 Vol 3A) used in the effective to physical address translation mechanisms (p4-28 Vol 3A) can be cached by TLBs and other Address Caching H/W structures accoring to Section 4.10 "CACHING TRANSLATION INFORMATION".


During effective ("linear") to physical address mapping, the system consults first the approriate TLB and likely other "Paging Structure Caches" to see if the mapping is already cached there.

If not, it traverses the page table hierarchies on DRAM (p4-28 Vol 3A) to locate this information. When the professor retrieves this page table information, do the cache memories (L3/L2/L1) of the core(s) cache any of this information ? Or does this traversal take place outside the regular load data from memory path ?

In case this information is cached within the regular data caches of the cores I would be interested to find out how much space they occupy there.


I would appreciate any information or pointer to it ....

thanks
Michael
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drMikeT
New Contributor I
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Is the memory controller and GlobalQueue architecture on SandyBridge different from those on Westmere?
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