Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Tsc-deadline feature. Cpu family ?

JLie
Beginner
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Hello,

I know that the tsc-deadline ( != tsc) feature has been added on recent intel cpu.

My question is:  on which families ?

Thanks !

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Patrick_F_Intel1
Employee
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Hello Jog,

From the SDM volume 3, chapter 35 (https://www-ssl.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf), it looks like it was added in starting with silvermont-based cpus on the atom side and sandybridge-based cpus on the big core side.

It is now an architectural MSR (table 35-2). There is a cpuid feature bit (see below) you can test to see if any cpu you are using supports IA32_TSC_DEADLINE. This is the preferred way of checking for support (rather than trying to track cpu family/models).

  • msr hex=6E0H
  • msr name=IA32_TSC_DEADLINE
  • desc=TSC Target of Local APIC’s TSC Deadline
  • Mode (R/W)
  • Test if exists on this cpu: If( CPUID.01H:ECX.[24] = 1

Pat

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JLie
Beginner
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Waw,

Well spotted Pat,

Thanks a lot !

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