Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
Announcements
FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.

Understanding PCIe bandwidth

Balsley__Elliott
Beginner
1,413 Views

Hello.  I'm trying to understand the results of pcm-pcie.  I read the Bytes option will multiply the number of transfers by 64 Bytes.  So in this case it would be 11M (PCIeRdCur) times 64B, which would be 704MB.  However, the PCIe Rd (B) column shows a much larger number 3323M.  How does this math work?

 

Also, socket 0 shows more transfers in the PCIeRdCur column, but socket 1 shows more data in the Bytes column.  I don't understand.

 

Skt | PCIeRdCur |  RFO  |  CRd  |  DRd  |  ItoM  |  PRd  |  WiL  | PCIe Rd (B) | PCIe Wr (B)
 0      11 M       380 K    18 M    21 M   3110 K    18 K  9336          3323 M         223 M
 1    2443 K        97 K    28 M    39 M   3110 K   216      65 K        4518 M         205 M
----------------------------------------------------------------------------------------------------
 *      14 M       478 K    47 M    60 M   6220 K    18 K    75 K        7841 M         428 M

 

0 Kudos
0 Replies
Reply