User cannot run PCM even though MSRs are R+W by Public

[drMikeT]

Hello 

I am using version 2.6 on RHEL 6u4. I have changed the permissions of all MSRs to +r+w by public but when I try to run ./pcm.x 1 as a common user, I am getting the following (I can run OK as root). 

Any suggestions?

Thanks

Michael

IntelPerformanceCounterMonitorV2.6 $  ./pcm.x  1

 Intel(r) Performance Counter Monitor V2.6 (2013-11-04 13:43:31 +0100 ID=db05e43)

 Copyright (c) 2009-2013 Intel Corporation

Number of physical cores: 16
Number of logical cores: 16
Threads (logical cores) per physical core: 1
Num sockets: 2
Core PMU (perfmon) version: 3
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Can not access CPUs Model Specific Registers (MSRs).
Try to execute 'modprobe msr' as root user and then
you also must have read and write permissions for /dev/cpu/*/msr devices (/dev/msr* for Android). The 'chown' command can help.
Access to Intel(r) Performance Counter Monitor has denied (no MSR or PCI CFG space access).

But MSRs are already R, W by  public :

IntelPerformanceCounterMonitorV2.6 $ ll /dev/cpu/*/msr
crw-rw-rw- 1 root root 202,  0 Jul 28 17:25 /dev/cpu/0/msr
...
crw-rw-rw- 1 root root 202, 15 Jul 28 17:25 /dev/cpu/15/msr

[drMikeT]

Note:

uname -r = 2.6.32-431.20.3.el6.x86_64 

[Thomas_W_Intel · Accepted solution]

Thank you for your report. We have encountered issues on newer kernels, where some of the access rights management has been changed. There, you need to set "

sudo setcap cap_sys_rawio=ep pcm.x

However, I'm surprised to see issues on older kernels as well. Has Redhat backported this restriction?

[drMikeT]

Hi Thomas,

thanks for the reply.

There is then NO need to chmod o+r,o+w on the /dev/cpu/*/msr devices ?

BTW, on an 2.6.32-279.25.2.el6.x86_64 kernel, running as root I am getting (see below). Any suggestions ?

Thanks!

Michael

#  /SOME/IntelPerformanceCounterMonitorV2.6/pcm.x 1 

 Intel(r) Performance Counter Monitor V2.6 (2013-11-04 13:43:31 +0100 ID=db05e43)

 Copyright (c) 2009-2013 Intel Corporation

Number of physical cores: 16
Number of logical cores: 16
Threads (logical cores) per physical core: 1
Num sockets: 2
Core PMU (perfmon) version: 3
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 2600000000 Hz
Package thermal spec power: 115 Watt; Package minimum power: 51 Watt; Package maximum power: 180 Watt; 
Socket 0: 1 memory controllers detected with total number of 4 channels. 2 QPI ports detected.
Socket 1: 1 memory controllers detected with total number of 4 channels. 2 QPI ports detected.
Using PCM on your system might have a performance impact as per http://software.intel.com/en-us/articles/performance-impact-when-sampling-certain-llc-events-on-snb-ep-with-vtune
You can avoid the performance impact by using the option --noJKTWA, however the cache metrics might be wrong then.
ERROR: QPI LL counter programming seems not to work. Q_P0_PCI_PMON_BOX_CTL=0xffffffff
       Please see BIOS options to enable the export of performance monitoring devices (devices 8 and 9: function 2).
ERROR: QPI LL counter programming seems not to work. Q_P1_PCI_PMON_BOX_CTL=0xffffffff
       Please see BIOS options to enable the export of performance monitoring devices (devices 8 and 9: function 2).
ERROR: QPI LL counter programming seems not to work. Q_P0_PCI_PMON_BOX_CTL=0xffffffff
       Please see BIOS options to enable the export of performance monitoring devices (devices 8 and 9: function 2).
ERROR: QPI LL counter programming seems not to work. Q_P1_PCI_PMON_BOX_CTL=0xffffffff
       Please see BIOS options to enable the export of performance monitoring devices (devices 8 and 9: function 2).
Max QPI link speed: 16.0 GBytes/second (8.0 GT/second)

Detected Intel(R) Xeon(R) CPU E5-2670 0 @ 2.60GHz "Intel(r) microarchitecture codename Sandy Bridge-EP/Jaketown"

[Roman_D_Intel]

Thomas explained the issue with QPI LL here.

[Roman_D_Intel]

I believe "chmod o+r,o+w on the /dev/cpu/*/msr" is still required.

[Bernard]

Seems that counters were locked by the BIOS.

[drMikeT]

Roman Dementiev (Intel) wrote:

I believe "chmod o+r,o+w on the /dev/cpu/*/msr" is still required.

Thanks Roman, I've verified that indeed the MSRs should be readable and writeable by public.

Mike

[drMikeT]

Roman Dementiev (Intel) wrote:

Thomas explained the issue with QPI LL here.

Thanks, I've made a request to get access to the BIOS guides pdf.

Mike