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WJ_C_
Beginner
466 Views

Viewing Skylake C-state C8/C9/10 using PCM v2.9

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For Windows, how to add support for C8/C9/C10 residency?

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Roman_D_Intel
Employee
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The output suggests that it is not the problem with monitoring. According to your PCM output the processor does not go into deeper package C states. The deepest is C6 (33.07 %). Which Windows version are you running?

Roman

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6 Replies
Roman_D_Intel
Employee
466 Views

could you post the pcm.exe output here? The expectation is that they are shown.

WJ_C_
Beginner
466 Views
C:\Program Files\PCM>pcm
DEBUG: Setting Ctrl+C done.

 Intel(r) Performance Counter Monitor V2.9+WJ (2015-09-28)

 Copyright (c) 2009-2015 Intel Corporation

Starting MSR service failed with error 2 Trying to load winring0.dll/winring0.sys driver...
Using winring0.dll/winring0.sys driver.

Number of physical cores: 2
Number of logical cores: 4
Number of online logical cores: 4
Threads (logical cores) per physical core: 2
Num sockets: 1
Physical cores per socket: 2
Core PMU (perfmon) version: 4
Number of core PMU generic (programmable) counters: 4
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 1500000000 Hz
Package thermal spec power: 4 Watt; Package minimum power: 0 Watt; Package maximum power: 0 Watt;

Detected Intel(R) Core(TM) m7-6Y75 CPU @ 1.20GHz "Intel(r) microarchitecture codename Skylake U/Y"

 EXEC  : instructions per nominal CPU cycle
 IPC   : instructions per CPU cycle
 FREQ  : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
 AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state'  (includes Intel Turbo Boost)
 L3MISS: L3 cache misses
 L2MISS: L2 cache misses (including other core's L2 cache *hits*)
 L3HIT : L3 cache hit ratio (0.00-1.00)
 L2HIT : L2 cache hit ratio (0.00-1.00)
 L3MPI : number of L3 cache misses per instruction
 L2MPI : number of L2 cache misses per instruction
 READ  : bytes read from memory controller (in GBytes)
 WRITE : bytes written to memory controller (in GBytes)
 IO    : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
 TEMP  : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature


 Core (SKT) | EXEC | IPC  | FREQ  | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3MPI | L2MPI |  READ | WRITE |  IO   | TEMP |

   0    0     0.01   0.31   0.02    0.27      79 K    111 K    0.26    0.42    0.01    0.01     N/A     N/A     N/A     72
   1    0     0.00   0.35   0.01    0.27      22 K     33 K    0.33    0.36    0.01    0.01     N/A     N/A     N/A     72
   2    0     0.00   0.21   0.01    0.28      30 K     45 K    0.28    0.33    0.01    0.01     N/A     N/A     N/A     74
   3    0     0.01   0.61   0.02    0.27     197 K    289 K    0.31    0.64    0.01    0.01     N/A     N/A     N/A     74
-----------------------------------------------------------------------------------------------------------------------------
 SKT    0     0.01   0.42   0.01    0.27     329 K    480 K    0.30    0.57    0.01    0.01    0.00    0.00    0.00     73
-----------------------------------------------------------------------------------------------------------------------------
 TOTAL  *     0.01   0.42   0.01    0.27     329 K    480 K    0.30    0.57    0.01    0.01    0.00    0.00    0.00     N/A

 Instructions retired:   36 M ; Active cycles:   88 M ; Time (TSC): 1517 Mticks ; C0 (active,non-halted) core residency: 5.32 %

 C1 core residency: 9.01 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 85.67 %;
 C2 package residency: 42.34 %; C3 package residency: 0.27 %; C6 package residency: 33.07 %; C7 package residency: 0.00 %; C8 package residency: 0.00 %; C9 package residency: 0.00 %; C10 package residency: 0.00 %;

 PHYSICAL CORE IPC                 : 0.83 => corresponds to 20.85 % utilization for cores in active state
 Instructions per nominal CPU cycle: 0.01 => corresponds to 0.30 % core utilization over time interval
----------------------------------------------------------------------------------------------

          package/CPU energy (Joules)  DIMM energy (Joules)
----------------------------------------------------------------------------------------------
 SKT    0              0.60                   N/A
----------------------------------------------------------------------------------------------

 

WJ_C_
Beginner
466 Views

How to make C8/C9/C10 available to Windows perfmon?

Roman_D_Intel
Employee
467 Views

The output suggests that it is not the problem with monitoring. According to your PCM output the processor does not go into deeper package C states. The deepest is C6 (33.07 %). Which Windows version are you running?

Roman

View solution in original post

WJ_C_
Beginner
466 Views

I am running it in Windows 10 build 10240.

Roman_D_Intel
Employee
466 Views

Could you try to find any energy settings in Windows 10? Sorry, I am not that familiar with Windows.

Thank you,

Roman

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