I have been reading the Intel developer manual (https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf) lately and have come across the term cacheline boundaries mentioned in the AVX section.
However, I am unsure what exactly a cacheline boundary means?
Does it mean the point where consecutive memory addresses get split across caches? For instance if address 200 in L1 and address 201 was in L2, accessing an 4 bytes starting from 200 would be a cache line boundary access?
Does it mean alignment basically? That is when a cache's well defined boundaries per data element (such as a word or quadword) for every few fixed number of bytes are crossed?
"Cache line splits" are the first scenario: You are loading or write a data elements where some part of the data is one cache line and the remaining part is in the adjacent cache line.
On Intel architecture, cache lines are 64B. Cache lines therefore start at a multiple of 64. So, in your example, it would be rather that 0x200 is one cache line and 0x0240 is the next cache line. If you read a DWORD from 0x23f, you have a cache line split.
Please note that, if all your data is aligned, you don't have cache line splits.